Contents
Using This Manual iii
Audience iii
How this Manual is Organized iii
Related Documents iii
Conventions iv
Obtaining Customer Support vi
Other Sources of Information vi
Contents vii
Introducing Star-Hspice 1-1
Star-Hspice Applications 1-2
Star-Hspice Features 1-3
Star-Hspice Platforms 1-6
Examining the Simulation Structure 1-7
Understanding the Data Flow 1-9
Simulation Process Overview 1-10
Getting Started 2-1
AC Analysis of an RC Network 2-2
Transient Analysis of an RC Network 2-5
Transient Analysis of an Inverter 2-7
Specifying Simulation Input and Controls 3-1
Using Netlist Input Files 3-2
Input Netlist File (
<design>.sp
) Guidelines 3-2
Input Netlist File Sections and Chapter References 3-7
Input Netlist File Composition 3-9
Title of Simulation and .TITLE Statement 3-9
Comments 3-9
Element and Source Statements 3-10
.SUBCKT or .MACRO Statement 3-12
.ENDS or .EOM Statement 3-14
Subcircuit Call Statement 3-14
Element and Node Naming Conventions 3-16
.GLOBAL Statement 3-19
.TEMP Statement 3-20
.DATA Statement 3-21
.INCLUDE Statement 3-29
.MODEL Statement 3-30
.LIB Call and Definition Statements 3-32
.OPTIONS SEARCH Statement 3-36
.PARAM Statement 3-37
.PROTECT Statement 3-40
.UNPROTECT Statement 3-40
.ALTER Statement 3-40
.DEL LIB Statement 3-42
.END Statement 3-45
Using Subcircuits 3-47
Hierarchical Parameters 3-48
Undefined Subcircuit Search 3-49
Discrete Device Libraries 3-50
DDL Library Access 3-50
Vendor Libraries 3-51
Subcircuit Library Structure 3-52
Using Standard Input Files 3-53
Design and File Naming Conventions 3-53
Configuration File (
meta.cfg
) 3-54
Initialization File (
hspice.ini
) 3-54
DC Operating Point Initial Conditions File (
<design>.ic
) 3-54
Output Files 3-55
Using the Star-Hspice Command 3-58
Prompting Script Mode 3-58
Nonprompting Command Line Mode 3-59
Improving Simulation Performance Using Multithreading 3-63
Running Star-Hspice-MT 3-63
Performance Improvement Estimations 3-64
Using Elements 4-1
Passive Elements 4-2
Resistors 4-2
Capacitors 4-4
Inductors 4-6
Mutual Inductors 4-9
Active Elements 4-12
Diode Element 4-12
Bipolar Junction Transistors (BJTs) Element 4-14
JFETs and MESFETs 4-16
MOSFETs 4-18
Transmission Lines 4-21
W Element Statement 4-21
T Element Statement 4-23
U Element Statement 4-25
Buffers 4-27
Using Sources and Stimuli 5-1
Independent Source Elements 5-2
Source Element Conventions 5-2
Independent Source Element 5-2
Star-Hspice Independent Source Functions 5-7
Pulse Source Function 5-7
Sinusoidal Source Function 5-10
Exponential Source Function 5-13
Piecewise Linear (PWL) Source Function 5-15
Data Driven Piecewise Linear Source Function 5-18
Single-Frequency FM Source Function 5-20
Amplitude Modulation Source Function 5-22
Using Voltage and Current Controlled Elements 5-24
Polynomial Functions 5-24
Piecewise Linear Function 5-28
Voltage Dependent Voltage Sources -- E Elements 5-29
Voltage Controlled Voltage Source (VCVS) 5-29
Behavioral Voltage Source 5-29
Ideal Op-Amp 5-29
Ideal Transformer 5-30
Voltage Dependent Current Sources -- G Elements 5-34
Voltage Controlled Current Source (VCCS) 5-34
Behavioral Current Source 5-34
Voltage Controlled Resistor (VCR) 5-35
Voltage Controlled Capacitor (VCCAP) 5-35
Dependent Voltage Sources -- H Elements 5-42
Current Controlled Voltage Source -- (CCVS) 5-42
Current Dependent Current Sources -- F Elements 5-46
Current Controlled Current Source (CCCS) 5-46
Digital and Mixed Mode Stimuli 5-50
U Element Digital Input Elements and Models 5-50
Specifying a Digital Vector File 5-60
Defining Tabular Data 5-64
Defining Vector Patterns 5-67
Modifying Waveform Characteristics 5-73
Multi-Terminal Networks 6-1
Using Scattering Parameter Element 6-2
Frequency Table Model 6-4
Parameters and Functions 7-1
Using Parameters in Simulation 7-2
Parameter Definition 7-2
Parameter Assignment 7-3
User-Defined Function Parameters 7-4
Subcircuit Default Definitions 7-5
Predefined Analysis Function 7-6
Measurement Parameters 7-6
Multiply Parameter 7-7
Using Algebraic Expressions
7-8
Algebraic Expressions for Output 7-8
Built-In Functions 7-9
User-Defined Functions 7-11
Parameter Scoping and Passing 7-13
Library Integrity 7-13
Reusing Cells 7-14
Creating Parameters in a Library 7-14
Parameter Defaults and Inheritance 7-17
Parameter Passing Problems 7-19
Specifying Simulation Output 8-1
Using Output Statements 8-2
Output Commands 8-2
Output Variables 8-3
Displaying Simulation Results 8-5
.PRINT Statement 8-5
.PLOT Statement 8-8
.PROBE Statement 8-9
.GRAPH Statement 8-10
Print Control Options 8-14
Subcircuit Output Printing 8-19
Selecting Simulation Output Parameters 8-21
DC and Transient Output Variables 8-21
AC Analysis Output Variables 8-29
Element Template Output 8-35
Specifying User-Defined Analysis (.MEASURE) 8-37
Measure Parameter Types 8-38
.MEASURE Statement: Rise, Fall, and Delay 8-39
FIND and WHEN Functions 8-43
Equation Evaluation 8-45
Average, RMS, MIN, MAX, INTEG, and Peak-To-Peak 8-46
INTEGRAL Function 8-48
DERIVATIVE Function 8-48
ERROR Function 8-51
Element Template Listings 8-55
Specifying Simulation Options 9-1
Setting Control Options 9-2
.OPTIONS Statement 9-2
General Control Options 9-5
Input and Output Options 9-5
CPU Options 9-11
Interface Options 9-11
Analysis Options 9-13
Error Options 9-15
Version Options 9-15
Model Analysis Options 9-16
General Options 9-16
MOSFET Control Options 9-18
Inductors 9-19
BJTs 9-19
Diodes 9-19
DC Operating Point, DC Sweep, and Pole/Zero 9-20
Accuracy 9-20
Matrix-Related 9-23
Input and Output 9-28
Convergence 9-29
Pole/Zero Control Options 9-35
Transient and AC Small Signal Analysis 9-38
Accuracy 9-38
Speed 9-41
Timestep 9-43
Input and Output 9-50
DC Initialization and Operating Point Analysis 10-1
Understanding the Simulation Flow 10-2
Performing Initialization and Analysis 10-3
Setting Initial Conditions for Transient Analysis 10-5
Using DC Initialization and Operating Point Statements 10-6
.OP Statement -- Operating Point 10-6
Element Statement IC Parameter 10-9
.IC and .DCVOLT Initial Condition Statements 10-9
.NODESET Statement 10-10
Using .SAVE and .LOAD Statements 10-11
.DC Statement--DC Sweeps 10-14
Using Other DC Analysis Statements 10-19
.SENS Statement -- DC Sensitivity Analysis 10-19
.TF Statement -- DC Small-Signal Transfer Function Analysis 10-20
.PZ Statement-- Pole/Zero Analysis 10-21
Setting DC Initialization Control Options 10-22
Option Descriptions 10-22
Pole/Zero Analysis Options 10-31
Specifying Accuracy and Convergence 10-34
Accuracy Tolerances 10-34
Accuracy Control Options 10-36
Convergence Control Option Descriptions 10-36
Autoconverge Process 10-42
Reducing DC Errors 10-45
Shorted Element Nodes 10-47
Conductance Insertion Using DCSTEP 10-47
Floating Point Overflow 10-48
Diagnosing Convergence Problems 10-49
Nonconvergence Diagnostic Table 10-49
Traceback of Nonconvergence Source 10-51
Solutions for Nonconvergent Circuits 10-51
Performing Transient Analysis 11-1
Understanding the Simulation Flow 11-2
Understanding Transient Analysis 11-3
Initial Conditions for Transient Analysis 11-3
Using the .TRAN Statement 11-4
Using the .BIASCHK Statement 11-9
Understanding the Control Options 11-11
Method Options 11-11
Tolerance Options 11-15
Limit Options 11-20
Matrix Manipulation Options 11-23
Controlling Simulation Speed and Accuracy 11-25
Simulation Speed 11-25
Simulation Accuracy 11-25
Numerical Integration Algorithm Controls 11-29
Selecting Timestep Control Algorithms 11-32
Iteration Count Dynamic Timestep Algorithm 11-33
Local Truncation Error (LTE) Dynamic Timestep Algorithm 11-34
DVDT Dynamic Timestep Algorithm 11-34
User Timestep Controls 11-35
Performing Fourier Analysis 11-37
.FOUR Statement 11-38
.FFT Statement 11-41
FFT Analysis Output 11-44
AC Sweep and Small Signal Analysis 12-1
Understanding AC Small Signal Analysis 12-2
Using the .AC Statement 12-4
AC Control Options 12-7
Using Other AC Analysis Statements 12-9
.DISTO Statement -- AC Small-Signal Distortion Analysis 12-9
.NOISE Statement -- AC Noise Analysis 12-11
.SAMPLE Statement -- Noise Folding Analysis 12-13
.NET Statement - AC Network Analysis 12-14
Statistical Analysis and Optimization 13-1
Specifying Analytical Model Types 13-2
Simulating Circuit and Model Temperatures 13-4
Temperature Analysis 13-5
.TEMP Statement 13-6
Performing Worst Case Analysis 13-8
Model Skew Parameters 13-8
Performing Monte Carlo Analysis 13-14
Monte Carlo Setup 13-14
Monte Carlo Output 13-15
.PARAM Distribution Function Syntax 13-16
Monte Carlo Parameter Distribution Summary 13-18
Monte Carlo Examples 13-18
Worst Case and Monte Carlo Sweep Example 13-26
HSPICE Input File 13-26
Transient Sigma Sweep Results 13-28
Monte Carlo Results 13-30
Optimization 13-35
Optimization Control 13-36
Simulation Accuracy 13-36
Curve Fit Optimization 13-37
Goal Optimization 13-37
Performing Timing Analysis 13-37
Understanding the Optimization Syntax 13-38
Optimization Examples 13-44
MOS Level 3 Model DC Optimization 13-44
MOS Level 13 Model DC Optimization 13-48
RC Network Optimization 13-51
CMOS Tristate Buffer Optimization 13-55
BJT S Parameters Optimization 13-60
BJT Model DC Optimization 13-63
GaAsFET Model DC Optimization 13-67
MOS Op-amp Optimization 13-70
Using Passive Device Models 14-1
Resistor Device Model and Equations 14-2
Wire RC Model 14-2
Resistor Model Equations 14-5
Capacitor Device Model and Equations 14-9
Capacitance Model 14-9
Capacitor Device Equations 14-10
Inductor Device Model and Equations 14-12
Inductor Core Models 14-12
Magnetic Core Element Outputs 14-16
Inductor Device Equations 14-17
Jiles-Atherton Ferromagnetic Core Model 14-19
Using Diodes 15-1
Understanding the Diode Types 15-3
Using Diode Model Statements 15-4
Setting Control Options 15-4
Specifying Junction Diode Models 15-6
Using the Junction Model Statement 15-7
Using Junction Model Parameters 15-8
Providing Geometric Scaling for Diode Models 15-14
Defining Diode Models 15-16
Determining Temperature Effects on Junction Diodes 15-19
Using Junction Diode Equations 15-22
Using Junction DC Equations 15-23
Using Diode Capacitance Equations 15-25
Using Noise Equations 15-28
Temperature Compensation Equations 15-28
Using the Junction Cap Model 15-33
Setting Juncap Model Parameters 15-35
Theory 15-37
JUNCAP Model Equations 15-38
Using the Fowler-Nordheim Diode 15-48
Converting National Semiconductor Models 15-50
Using BJT Models 16-1
Using BJT Models 16-2
Selecting Models 16-2
Understanding the BJT Model Statement 16-4
Using BJT Basic Model Parameters 16-5
Handling BJT Model Temperature Effects 16-14
Using BJT Device Equivalent Circuits 16-20
Scaling 16-20
Understanding the BJT Current Convention 16-20
Using BJT Equivalent Circuits 16-21
Using BJT Model Equations (NPN and PNP) 16-28
Understanding Transistor Geometry in Substrate Diodes 16-28
Using DC Model Equations 16-29
Using Substrate Current Equations 16-31
Using Base Charge Equations 16-32
Using Variable Base Resistance Equations 16-32
Using BJT Capacitance Equations 16-34
Using Base-Emitter Capacitance Equations 16-34
Determining Base Collector Capacitance 16-36
Using Substrate Capacitance 16-38
Defining BJT Noise Equations 16-40
Using BJT Temperature Compensation Equations 16-42
Using Energy Gap Temperature Equations 16-42
Using Saturation and Beta Temperature Equations,
TLEV=0 or 2 16-42
Using Saturation and Temperature Equations, TLEV=1 16-44
Using Saturation Temperature Equations, TLEV=3 16-45
Using Capacitance Temperature Equations 16-46
Using Parasitic Resistor Temperature Equations 16-49
Using BJT LEVEL=2 Temperature Equations 16-49
Using the BJT Quasi-Saturation Model 16-50
Using Epitaxial Current Source Iepi 16-51
Using Epitaxial Charge Storage Elements Ci and Cx 16-52
Converting National Semiconductor Models 16-55
Using the VBIC Bipolar Transistor Model 16-57
Understanding the History of VBIC 16-57
VBIC Parameters 16-57
Noise Analysis 16-58
LEVEL 6 Philips Bipolar Model (MEXTRAM LEVEL 503) 16-68
LEVEL 6 Element Syntax 16-69
LEVEL 6 Model Parameters 16-69
LEVEL 6 Philips Bipolar Model (MEXTRAM LEVEL 504) 16-75
Notes for HSPICE Users 16-76
LEVEL 6 Model Parameters (504) 16-77
LEVEL 8 HiCUM Model 16-93
What is the HiCUM Model? 16-93
HiCUM Model Advantages 16-93
Star-Hspice HiCUM Model vs. Public HiCUM Model 16-95
Model Implementation 16-95
Internal Transistors 16-95
Using JFET and MESFET Models 17-1
Understanding JFETs 17-2
Specifying a Model 17-3
Understanding the Capacitor Model 17-5
Model Applications 17-5
Control Options 17-6
Using JFET and MESFET Equivalent Circuits 17-7
Scaling 17-7
Understanding JFET Current Convention 17-7
JFET Equivalent Circuits 17-8
Using JFET and MESFET Model Statements 17-13
JFET and MESFET Model Parameters 17-13
Gate Diode DC Parameters 17-15
JFET and MESFET Capacitances 17-25
Capacitance Comparison (CAPOP=1 and CAPOP=2) 17-29
JFET and MESFET DC Equations 17-31
JFET and MESFET Noise Models 17-35
Noise Parameters 17-35
Noise Equations 17-35
Noise Summary Printout Definitions 17-37
JFET and MESFET Temperature Equations 17-38
Temperature Compensation Equations 17-41
Using TriQuint Model (TOM) Extensions to LEVEL=3 17-45
TOM Model Parameters 17-46
Using Transmission Lines 18-1
Using Transmission Line Equations and Parameters 18-3
Using Frequency-Dependent Resistance and Conductance Matrices 18-4
Determining Matrix Properties 18-4
Understanding Wave Propagation on Transmission Lines 18-5
Propagating a Voltage Step in a Transmission Line 18-6
Handling Line-to-Line Junctions 18-8
Using the W Element 18-10
W Element and Field Solver Updates 18-12
W Element Transmission Line Properties Inputs 18-14
Tabular RLGC Model for W Element 18-27
W Element Syntax for a Tabular RLGC Model 18-27
Tabular RLGC Model Syntax 18-28
Extracting Transmission Line Parameters 18-34
Filament Method 18-34
Modeling Geometries 18-35
Solver Limitations 18-36
Using the Field-Solver Statement Syntax 18-36
Defining Material Properties 18-36
Creating Layer Stacks 18-37
Defining Shapes 18-38
Field-Solver Options 18-42
Using the Field Solver Model 18-43
Field Solver Examples 18-45
Example 1: Cylindrical Conductor Above a Ground Plane 18-45
Example 2: Stratified Dielectric Media 18-47
Example 3: Two Traces Between Two Ground Planes 18-50
Example 4: Using Field Solver with Monte Carlo Analysis 18-52
Using IBIS Models 19-1
Understanding IBIS Conventions 19-3
Terminology 19-4
Limitations and Restrictions 19-5
Buffers 19-6
Input Buffer 19-6
Output Buffer 19-8
Tristate Buffer 19-11
Input/Output Buffer 19-15
Open Drain, Open Sink, Open Source Buffers 19-18
I/O Open Drain, I/O Open Sink, I/O Open Source Buffers 19-18
Input ECL Buffer 19-19
Output ECL Buffer 19-20
Tristate ECL Buffer 19-21
Input-Output ECL Buffer 19-23
Specifying Common Keywords 19-26
Required Keywords 19-26
Optional Keywords 19-26
Differential Pins 19-36
Scaling Buffer Strength 19-38
Buffers in subcircuits 19-39
Example 19-42
Additional Notes 19-44
Keywords 19-44
Voltage Thresholds 19-44
.OPTION D_IBIS 19-44
Understanding Warning and Error Messages 19-46
References 19-49
Introducing MOSFETs 20-1
Understanding MOSFET Models 20-3
Selecting Models 20-4
Selecting MOSFET Model LEVELs 20-4
Selecting MOSFET Capacitors 20-7
Selecting MOS Diodes 20-9
Setting MOSFET Control Options 20-11
Using the General MOSFET Model Statement 20-14
Using Nonplanar and Planar Technologies 20-15
Using Field Effect Transistors 20-16
Using MOSFET Equivalent Circuits 20-20
Using a MOSFET Diode Model 20-26
Selecting MOSFET Diode Models 20-26
Enhancing Convergence 20-26
Using MOSFET Diode Model Parameters 20-27
Using an ACM=0 MOS Diode 20-31
Using an ACM=1 MOS Diode 20-34
Using an ACM=2 MOS Diode 20-37
Using an ACM=3 MOS Diode 20-41
Using MOS Diode Equations 20-45
DC Current 20-45
Using MOS Diode Capacitance Equations 20-46
Using Common Threshold Voltage Equations 20-50
Common Threshold Voltage Parameters 20-50
Calculating PHI, GAMMA, and VTO 20-51
Performing MOSFET Impact Ionization 20-53
Using Impact Ionization Model Parameters 20-53
Calculating the Impact Ionization Equations 20-53
Calculating Effective Output Conductance 20-54
Cascoding Example 20-55
Cascode Circuit 20-56
Using MOS Gate Capacitance Models 20-57
Selecting Capacitor Models 20-57
Introducing Transcapacitance 20-59
Using the Operating Point Capacitance Printout 20-61
Using the Element Template Printout 20-62
Calculating Gate Capacitance 20-64
Using MOS Gate Capacitance Model Parameters 20-69
Specifying XQC and XPART for CAPOP=4, 9, 11, 12 and 13 20-72
Using Overlap Capacitance Equations 20-73
Defining CAPOP=0 -- SPICE Meyer Gate Capacitances 20-74
Defining CAPOP=1 -- Modified Meyer Gate Capacitances 20-77
Defining CAPOP=2--Parameterized Modified Meyer Capacitances 20-81
Defining CAPOP=3 -- Gate Capacitances (Simpson Integration) 20-86
Defining CAPOP=4 -- Charge Conservation Capacitance Model 20-87
Defining CAPOP=5 -- Gate Capacitance 20-94
Defining CAPOP=6 -- AMI Gate Capacitance Model 20-94
Defining CAPOP=13 -- BSIM1-based Charge-Conserving Gate Capacitance Model 20-97
Defining CAPOP=39 -- BSIM2 Charge-Conserving Gate Capacitance Model 20-97
Calculating Effective Length and Width for AC Gate Capacitance 20-97
Using Noise Models 20-99
Using Noise Parameters 20-99
Using Noise Equations 20-99
Noise Summary Printout Definitions 20-101
Using Temperature Parameters and Equations 20-102
Temperature Parameters 20-102
Using Temperature Equations 20-105
Selecting MOSFET Models: LEVEL 1-40 21-1
LEVEL 1 IDS: Schichman-Hodges Model 21-2
LEVEL 1 Model Parameters 21-2
LEVEL 1 Model Equations 21-5
LEVEL 2 IDS: Grove-Frohman Model 21-7
LEVEL 2 Model Parameters 21-7
LEVEL 2 Model Equations 21-11
LEVEL 3 IDS: Empirical Model 21-19
LEVEL 3 Model Parameters 21-19
LEVEL 3 Model Equations 21-22
Compatibility Notes 21-29
Temperature Compensation 21-30
LEVEL 4 IDS: MOS Model 21-33
LEVEL 5 IDS Model 21-34
LEVEL 5 Model Parameters 21-34
IDS Equations 21-37
Depletion Mode DC Model ZENH=0 21-42
IDS Equations, Depletion Model LEVEL 5 21-43
LEVEL 6 and LEVEL 7 IDS: MOSFET Model 21-52
LEVEL 6 and LEVEL 7 Model Parameters 21-52
UPDATE Parameter for LEVEL 6 and LEVEL 7 21-57
LEVEL 6 Model Equations, UPDATE=0,2 21-60
LEVEL 6 IDS Equations, UPDATE=1 21-71
ASPEC Compatibility 21-86
LEVEL 7 IDS Model 21-88
LEVEL 8 IDS Model 21-89
LEVEL 8 Model Parameters 21-89
LEVEL 8 Model Equations 21-93
LEVEL 13 BSIM Model 21-101
BSIM Model Features 21-101
LEVEL 13 Model Parameters 21-102
Sensitivity Factors of Model Parameters 21-109
.MODEL VERSION Changes to BSIM Models 21-111
LEVEL 13 Equations 21-112
Charge-Based Capacitance Model 21-117
Prevention of Negative Output Conductance 21-121
Calculations Using LEVEL 13 Equations 21-121
Compatibility Notes 21-123
LEVEL 27 SOSFET Model 21-136
LEVEL 27 Model Parameters 21-138
Non-Fully Depleted SOI Model 21-142
Obtaining Model Parameters 21-143
Fully Depleted SOI Model Considerations 21-146
LEVEL 28 Modified BSIM Model 21-147
LEVEL 28 Model Parameters 21-147
LEVEL 28 Model Equations 21-155
LEVEL 38 IDS: Cypress Depletion Model 21-162
LEVEL 38 Model Parameters 21-164
LEVEL 38 Model Equations 21-169
Example Model File 21-177
LEVEL 39 BSIM2 Model 21-179
LEVEL 39 Model Parameters 21-179
LEVEL 39 Model Equations 21-186
Geometry and Bias Adjustment of Model Parameters 21-190
Compatibility Notes 21-191
Prevention of Negative Output Conductance 21-193
Charge-based Gate Capacitance Model (CAPOP=39) 21-194
Star-Hspice Enhancements 21-196
Modeling Example 21-200
Typical BSIM2 Model Listing 21-203
LEVEL 40 HP a-Si TFT Model 21-207
Model Parameters 21-207
Using the HP a-Si TFT Model in Star-Hspice 21-208
LEVEL 40 Model Equations 21-211
LEVEL 40 Model Topology 21-217
Comparing MOS Models 21-218
History and Motivation 21-218
Future for Model Developments 21-220
Model Equation Evaluation Criteria 21-221
Potential for Good Fit to Data 21-221
Ease of Fit to Data 21-222
Robustness and Convergence Properties 21-223
Behavior Follows Actual Devices In All Circuit Conditions 21-224
Ability to Simulate Process Variation 21-225
Gate Capacitance Modeling 21-225
Examples of Data Fitting 21-227
Selecting MOSFET Models: LEVEL 47-62 22-1
LEVEL 47 BSIM3 Version 2 MOS Model 22-2
LEVEL 47 Model Parameters 22-2
Leff and Weff Equations for BSIM3 Version 2.0 22-9
LEVEL 47 Model Equations 22-10
PMOS Model 22-18
LEVELs 49 and 53 BSIM3v3 MOS Models 22-19
Selecting Model Versions 22-20
Version 3.2 Features 22-22
Nonquasi-Static (NQS) Model 22-23
Star-Hspice Enhancements 22-24
Using BSIM3v3 in Star-Hspice 22-32
LEVEL 49, 53 Model Parameters 22-34
Parameter Range Limits 22-49
LEVEL 49, 53 Equations 22-52
.MODEL CARDS NMOS Model 22-53
PMOS Model 22-55
LEVEL 50 Philips MOS9 Model 22-56
LEVEL 50 Model Parameters 22-56
22-61
JUNCAP Model Parameters 22-62
Using the Philips MOS9 Model in Star-Hspice 22-63
Star-Hspice Model Statement 22-64
LEVEL 54 BSIM4.0 Model 22-66
LEVEL 54 Model Parameters 22-67
LEVEL 55 EPFL-EKV MOSFET Model 22-85
Single Equation Model 22-85
Effects Modeled 22-85
Coherence of Static and Dynamic Models 22-86
Bulk Reference and Symmetry 22-86
Equivalent Circuit 22-87
Device Input Variables 22-88
EKV Intrinsic Model Parameters 22-88
Static Intrinsic Model Equations 22-92
Quasi-static Model Equations 22-103
Non-Quasi-Static (NQS) Model Equations 22-106
Intrinsic Noise Model Equations 22-107
Operating Point Information 22-108
Estimation and Limits of Static Intrinsic Model Parameters 22-109
Model Updates Description 22-111
LEVEL 57 UC Berkeley BSIM3-SOI Model 22-114
LEVEL 57 Model Parameters 22-117
LEVEL 57 Template Output 22-128
LEVEL 57 Updates to BSIM3-SOI PD versions 2.2, 2.21, and 2.22 22-131
LEVEL 58 University of Florida SOI Model 22-133
LEVEL 58 FD/SOI MOSFET Model Parameters 22-134
LEVEL 58 NFD/SOI MOSFET Model Parameters 22-138
LEVEL 58 Template Output 22-144
LEVEL 59 UC Berkeley BSIM3-SOI FD Model 22-147
LEVEL 59 Model Parameters 22-149
LEVEL 59 Template Output 22-157
LEVEL 60 UC Berkeley BSIM3-SOI DD Model 22-161
Model Features 22-161
Syntax 22-162
Level 60 Model Parameters 22-164
LEVEL 61 RPI a-Si TFT Model 22-175
Model Features 22-175
Using LEVEL 61 with Star-Hspice 22-175
LEVEL 61 Model Parameters 22-176
Equivalent Circuit 22-178
Model Equations 22-178
LEVEL 62 RPI Poli-Si TFT Model 22-182
Model Features 22-182
Using LEVEL 62 with Star-Hspice 22-183
LEVEL 62 Model Parameters 22-184
Equivalent Circuit 22-186
Model Equations 22-186
Using the Common Model Interface 23-1
Understanding CMI 23-2
Examining the Directory Structure 23-3
Running Simulations with CMI Models 23-4
Supported Platforms 23-5
Adding Proprietary MOS Models 23-6
Creating a CMI Shared Library 23-6
Testing CMI Models 23-12
Model Interface Routines 23-13
Interface Variables 23-18
pModel, pInstance 23-19
CMI_ResetModel 23-20
CMI_ResetInstance 23-22
CMI_AssignModelParm 23-22
CMI_AssignInstanceParm 23-23
CMI_SetupModel 23-24
CMI_SetupInstance 23-25
CMI_Evaluate 23-26
CMI_DiodeEval 23-27
CMI_Noise 23-29
CMI_PrintModel 23-31
CMI_FreeModel 23-32
CMI_FreeInstance 23-32
CMI_WriteError 23-33
CMI_Start 23-35
CMI_Conclude 23-35
CMI Function Calling Protocol 23-36
Internal Routines 23-38
Supporting Extended Topology 23-40
Conventions 23-42
Bias Polarity Conventions for N- and P-channel Devices 23-42
Source-Drain Reversal Conventions 23-43
Thread-Safe Model Code 23-44
Performing Cell Characterization 24-1
Determining Typical Data Sheet Parameters 24-2
Rise, Fall, and Delay Calculations 24-2
Ripple Calculation 24-3
Sigma Sweep versus Delay 24-4
Delay versus Fanout 24-5
Pin Capacitance Measurement 24-6
Op-amp Characterization of ALM124 24-7
Cell Characterization Using Data Driven Analysis 24-9
Signal Integrity 25-1
Preparing for Simulation 25-2
Signal Integrity Problems 25-3
Analog Side of Digital Logic 25-4
Optimizing TDR Packaging 25-9
TDR Optimization Procedure 25-11
Simulating Circuits with Signetics Drivers 25-18
Simulating Circuits with Xilinx FPGAs 25-22
Ground Bounce Simulation 25-24
Coupled Line Noise 25-27
PCI Modeling Using Star-Hspice 25-33
Importance of Star-Hspice Simulation to PCI Design 25-35
PCI Speedway Star-Hspice Model 25-35
Reference PCI Speedway Model, PCI_WC.SP 25-38
PCI Simulation Process 25-45
Performing Behavioral Modeling 26-1
Understanding the Behavioral Design Process 26-2
Using Behavioral Elements 26-3
Using Voltage and Current Controlled Elements 26-6
Polynomial Functions 26-7
Piecewise Linear (PWL) Function 26-10
Dependent Voltage Sources -- E Elements 26-11
Voltage Controlled Voltage Source (VCVS) 26-11
Behavioral Voltage Source 26-11
Ideal Op-Amp 26-11
Ideal Transformer 26-12
Dependent Current Sources -- G Elements 26-16
Voltage Controlled Current Source (VCCS) 26-16
Behavioral Current Source 26-16
Voltage Controlled Resistor (VCR) 26-16
Voltage Controlled Capacitor (VCCAP) 26-17
Dependent Voltage Sources - H Elements 26-23
Current Controlled Voltage Source (CCVS) 26-23
Current Dependent Current Sources -- F Elements 26-27
Current Controlled Current Source (CCCS) 26-27
Modeling with Digital Behavioral Components 26-31
Behavioral AND and NAND Gates 26-31
Behavioral D-Latch 26-32
Behavioral Double-Edge Triggered Flip-Flop 26-36
Calibrating Digital Behavioral Components 26-40
Building Behavioral Lookup Tables 26-40
Optimizing Behavioral CMOS Inverter Performance 26-46
Optimizing Behavioral Ring Oscillator Performance 26-50
Using Analog Behavioral Elements 26-53
Behavioral Integrator 26-53
Behavioral Differentiator 26-55
Ideal Transformer 26-57
Behavioral Tunnel Diode 26-58
Behavioral Silicon Controlled Rectifier (SCR) 26-59
Behavioral Triode Vacuum Tube Subcircuit 26-60
Behavioral Amplitude Modulator 26-62
Behavioral Data Sampler 26-63
Using Op-Amps, Comparators, and Oscillators 26-65
Star-Hspice Op-Amp Model Generator 26-65
Op-Amp Element Statement Format 26-66
Op-Amp .MODEL Statement Format 26-66
Op-Amp Subcircuit Example 26-74
741 Op-Amp from Controlled Sources 26-76
Inverting Comparator with Hysteresis 26-79
Voltage Controlled Oscillator (VCO) 26-81
LC Oscillator 26-83
Using a Phase Locked Loop Design 26-88
Phase Detector Using Multi-Input NAND Gates 26-88
PLL BJT Behavioral Modeling 26-92
References 26-100
Performing Pole/Zero Analysis 27-1
Understanding Pole/Zero Analysis 27-2
Using Pole/Zero Analysis 27-3
.PZ (Pole/Zero) Statement 27-3
Pole/Zero Analysis Examples 27-5
Performing FFT Spectrum Analysis 28-1
Using Windows In FFT Analysis 28-3
Using the .FFT Statement 28-7
Examining the FFT Output 28-10
AM Modulation 28-13
Balanced Modulator and Demodulator 28-16
Signal Detection Test Circuit 28-24
References 28-29
Modeling Filters and Networks 29-1
Understanding Transient Modeling 29-2
Using G and E Elements 29-4
Laplace Transform Function Call 29-4
Element Statement Parameters 29-9
Laplace Band-Reject Filter 29-12
Laplace Low-Pass Filter 29-14
Circular Convolution Example 29-17
Laplace and Pole-Zero Modeling 29-20
Laplace Transform (LAPLACE) Function 29-20
Laplace Transform POLE (Pole/Zero) Function 29-28
AWE Transfer Function Modeling 29-35
Y Parameter Line Modeling 29-39
Comparison of Circuit and Pole/Zero Models 29-43
Modeling Switched Capacitor Filters 29-48
Switched Capacitor Network 29-48
Switched Capacitor Filter Example 29-50
References 29-55
Timing Analysis Using Bisection 30-1
Understanding Bisection 30-2
Understanding the Bisection Methodology 30-5
Measurement 30-5
Optimization 30-5
Using Bisection 30-6
Examining the Command Syntax 30-7
Setup Time Analysis 30-10
Minimum Pulse Width Analysis 30-16
Running Demonstration Files 31-1
Using the Demo Directory Tree 31-2
Running the Two-Bit Adder Demo 31-3
Running the MOS I-V and C-V Plotting Demo 31-7
Running the CMOS Output Driver Demo 31-12
Running the Temperature Coefficients Demo 31-18
Simulating Electrical Measurements 31-20
Modeling Wide-Channel MOS Transistors 31-23
Examining the Demonstration Input Files 31-26
FAQ/Troubleshooting A-1
Analysis A-2
Documentation A-4
Environment Variables A-6
Error Messages A-7
Input A-12
Installation Issues A-13
Licensing/Access Issues A-15
Limitations A-17
Miscellaneous A-18
Models A-20
MS Windows/PC Issues A-23
Netlist/Options A-27
Output A-32
W Element/Field Solver A-34
Waveform Viewing A-35
Interfaces For Design Environments B-1
AvanLink to Cadence Composer and Analog Artist B-2
Features B-2
Environment B-3
AvanLink Design Flow B-4
Schematic Entry and Library Operations B-5
Netlist Generation B-6
Simulation B-7
Waveform Display B-7
AvanLink for Design Architect B-8
Features B-8
Environment B-9
AvanLink-DA Design Flow B-10
Schematic Entry and Library Operations B-10
Netlist Generation B-12
Simulation B-12
Waveform Display B-12
Viewlogic Links B-13
Ideal and Lumped Transmission Lines C-1
Selecting Wire Models C-2
Using Ground and Reference Planes C-5
Selecting Ideal or Lossy Transmission Line Element C-5
Selecting U Models C-7
Using Transmission Lines - Example C-8
Performing Interconnect Simulation C-10
Using the Ideal Transmission Line C-10
Lossy U Element Statement C-11
Lossy U Model Statement C-12
Planar Geometric Models Lossy U Model Parameters C-14
Lossy U Model Parameters for Geometric Coax (PLEV=2, ELEV=1) C-25
Lossy U Model Parameters Geometric Twinlead (PLEV=3, ELEV=1) C-27
U Element Examples C-38
U Model Applications C-55
Solving Ringing Problems with U Elements C-60
Understanding the Transmission Line Theory C-70
Lossless Transmission Line Model C-70
Lossy Transmission Line Model C-71
Impedance C-72
Inductance C-75
Crosstalk in Transmission Lines C-78
Risetime, Bandwidth, and Clock Frequency C-79
Definitions of Transmission Line Terms C-81
Relationships and Rules of Thumb C-82
Attenuation in Transmission Lines C-88
The Lossy Transmission Line Model C-91
References C-95
Finding Device Libraries D-1
Selecting Models Automatically D-2
Examining the Library Listings D-5
Analog Device Models D-5
Behavioral Device Models D-8
Bipolar Transistor Models D-9
Burr-Brown Devices D-9
Comlinear Device Models D-10
Diode Models D-10
FET Models D-12
Linear Technology Device Models D-14
Intel PCI Speedway Models D-15
Signetics Device Models D-15
Texas Instruments Device Models D-16
Transmission Line Models D-17
Xilinx Device Models D-17
Performing Library Encryption E-1
Understanding Library Encryption E-2
Controlling the Encryption Process E-2
Library Structure E-2
Knowing the Encryption Guidelines E-5
Installing and Running the Encryptor E-7
Installing the Encryptor E-7
Running the Encryptor E-7
Understanding Metaencrypt Features E-9
New 8-Byte Key Encryption E-9
Encryption Structure E-9
Supporting the .sp File Encryption E-10
Supporting .lib File Encryption E-11
Supporting .inc File Encryption E-12
Supporting .load Encryption E-13
Supporting 80+ Columns Encryption E-13
Statements Not Supported E-13
Additional Recommendations for Encryption E-13
Complete Encryption Structure Example E-13
Full Simulation Examples F-1
Full Simulation Example with AvanWaves F-2
Input Netlist and Circuit F-2
Execution and Output Files F-4
Simulation Graphical Output in AvanWaves F-10
Full Simulation Example with Cosmos-Scope F-14
Input Netlist and Circuit F-14
Execution and Output Files F-16
Using Cosmos-Scope to View Star-Hspice Results F-16
Index -- All Volumes I-1
Star-Hspice Manual - Release 2001.2 - June 2001
