LEVEL 40 HP a-Si TFT Model

Star-Hspice LEVEL 40 is a Hewlett-Packard amorphous silicon thin-film transistor model.

Model Parameters

Using the HP a-Si TFT Model in Star-Hspice

1. Set LEVEL=40 to identify the model as the HP a-Si TFT model.

2. The default value for L is 10µm, and the default value for W is 40 µm.

3. Use the "M" designation for MOSFET rather than the "A" designation for a-Si TFT in the netlist.

4. Use the "NMOS" or "PMOS" designation for device type rather than the "NAT" or "PAT" designation.

Note: Because of the unavailability of p-channel TFTs, PMOS model testing has been very limited.

5. The LEVEL 40 model is a three-terminal model. No bulk node exists; therefore, no parasitic drain-bulk or source-bulk diodes are appended to the model. A fourth node can be specified, but does not affect simulation results (except for GMIN terms).

6. Parasitic resistances and overlap capacitances are constant. They are not scaled with width, length, and temperature.

7. The capacitance expressions in this model do not conserve charge.

8. The HP a-Si TFT model has a TREF parameter that is an exponent in an expression for mobility temperature dependence.

Other models use the BEX parameter for similar mobility temperature dependence expressions. The HP a-Si TFT TREF model parameter is not the same as the reference temperature TREF used in other models. The reference temperature for the HP a-Si TFT model is 312 K (or 38.85 o C), and cannot be modified. Experimental results from TFT manufacturers indicate that amorphous silicon materials are most stable at this temperature.

9. The default room temperature is 25 o C in Star-Hspice, but is 27 o C in some other simulators. It is a matter of choice whether or not to set the nominal simulation temperature to 27 o C, by adding .OPTION TNOM=27 to the netlist. Although the reference temperature of the HP
a-Si TFT model is fixed at 312 o K (or 38.85 o C), the behavior of the model adjusts to other simulation temperatures that are user specified or provided by Star-Hspice as defaults.

10. HP's SPICE3E2 implementation of this model, on which this implementation is based, is not temperature-dependent. The LEVEL 40 has temperature dependency enabled.

11. The default value of CAPOP is 40, which is the HP a-Si TFT non-charge-conserving capacitance model. CAPOP values of 0, 1, 2, 3, 4, 5, 9, 12, or 13 are allowed, but have not been thoroughly tested.

12. The default of DERIV is zero, the analytical method. DERIV can be set to 1 to select the finite difference method.

Effect of SCALE and SCALM

The SCALE option has the same effect for LEVEL 40 as for other Star-Hspice models, such as LEVEL 3 or LEVEL 28. If the values of L and W are in microns rather than meters (for example, L=1 rather than L=1µ or
1e-6), set .OPTION SCALE=1e-6.

The SCALM option is disabled in the LEVEL 40 model. For standard Star-Hspice models such as LEVEL 3, SCALM affects the scale of model parameters such as XL, XW, LD, WD, CJ, and CJSW.

Because the SCALM option is ignored by the LEVEL 40 model, LEVEL 40 models can be mixed in a simulation with other models in which the SCALM is set.

In general, netlists for Star-Hspice should be made as standard as possible. Also, it is best to convert L and W to meters scale instead of microns scale, so that the netlist can be used without the OPTION SCALE=1E-6. If these recommendations are followed, then a system-level Star-Hspice user can use
I/O subcircuits from different vendors in one simulation.

Noise Model

The LEVEL 40 model uses the standard NLEV=0 noise model inherited from Star-Hspice.

Element DELVTO

DELVTO and DTEMP on the element line can be used with LEVEL 40.

Star-Hspice Model and Element Statement Example

.MODEL nch nmos LEVEL=40 UO=0.4229 VTO=1.645 PHI=1.25 NSS=0

+ NFS=2.248E+21 VMAX=1231

+ THETA=-0.01771 ETA=0.0002703 T1=2.6E-07 T2=0 E1=3.9 E2=0

+ GO=9.206E-15 NU=0 K2=2 CHI=0.5

+ PSI=1E-20 VTIME=0.01 TREF=1.5 CGSO=5.203E-14 CGDO=4.43E-14

+ CSC=0.0001447 RD=5097

+ RS=5097 FREQ=1E+06 DEFF=2.15 TAU=1.64E-07 FEFF=0.5

MCKT 1 2 3 nch L=1e-05 W=4e-05

LEVEL 40 Model Equations

In the following equations, model parameters are shown in all capital letters; working variables are in lower case. Model parameters and bias voltages vgs and vds are inputs. Ids, gm, and gds are the DC outputs, and the gate-to-source capacitance Cgs and the gate-to-drain capacitance Cgd are the AC outputs. Electron charge is q, Boltzmann's constant is k, and the permittivity of a vacuum is .

Scaling by SCALE has been done prior to evaluation of the equations. Scaling by M is done after evaluation.

The variables and are intermediate, not final, quantities.

A complete description of TFT technology and the device physics underlying these equations can be found in the Hewlett-Packard HP IC-CAP manual.

Initially, , , , ,

If then

, the dielectric capacitance per unit area, is computed as follows:

If and , then

If and , then

If and , then

TEMP is the Star-Hspice device simulation temperature, specified in o C, but converted to o K internally for the evaluation of these equations.

If , then and .

(printback definition)

(printback definition)

(printback definition)

If and and and , then:

If , then:

Cutoff Region (NFS = 0, vgs <= von)

If and , then:

Noncutoff Region (NFS 0)

If , then:

If , then:

Mobility modulation by vgs:

If , then:

is the series combination of the dielectric and space charge capacitance of the MIS structure.

If vds < vdsat, then:

is the effective equivalent dielectric constant of the insulator layers.

Otherwise, :

If , then:

Normalized drain current:

Drain current without velocity saturation effect:

Velocity saturation factor--if , then:

Strong inversion current:

Weak inversion current--if , then:

:

If and , then

Cgd, Cgs

LEVEL 40 Model Topology

LEVEL 40 HP a-Si TFT Topology shows the topology of the LEVEL 40 model.

Figure 21-12: LEVEL 40 HP a-Si TFT Topology