Two MOSFET fabrication technologies have dominated integrated circuit design: nonplanar and planar technologies. Nonplanar technology uses metal gates. The simplicity of the process generally provides acceptable yields. The primary problem with metal gates is metal breakage across the field oxide steps. Field oxide is grown by oxidizing the silicon surface. When the surface is cut, it forms a sharp edge. Since metal must be affixed to these edges in order to contact the diffusion or make a gate, it is necessary to apply thicker metal to compensate for the sharp edges. This metal tends to gather in the cuts, making etching difficult. The inability to accurately control the metal width necessitates very conservative design rules and results in low transistor gains.
In planar technology, the oxide edges are smooth, with a minimal variance in metal thickness. Shifting to nitride was accomplished by using polysilicon gates. Adding a chemical reactor to the MOS fabrication process enables not only the deposition of silicon nitride, but also that of silicon oxide and polysilicon. The ion implanter is the key element in this processing, using implanters with beam currents greater than 10 milliamperes.
Since implanters define threshold voltages and "diffusions" as well as field thresholds, processes require a minimum number of high temperature oven steps. This enables low temperature processing and maskless pattern generation. The new wave processes are more similar to the older nonplanar metal gate technologies.
The metal gate MOSFET is nonisoplanar as shown in Field Effect Transistor and Field Effect Transistor Geometry.
Looking at the actual geometry, from source-to-drain, Field Effect Transistor Geometry shows a perspective of the nonisoplanar MOSFET.
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Drawn metal gate channel length |
To visualize the construction of the silicon gate MOSFET, observe how a source or drain to field cuts (Isoplanar Silicon Gate Transistor.) The cut A-B shows a drain contact (Isoplanar MOSFET Construction, Part A).
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Diffusion drawn dimension for nitride |
The cut from the source to the drain is represented by C - D (Isoplanar MOSFET Construction, Part B), which includes the contacts.
The planar process produces parasitic capacitances at the poly to field edges of the device. The cut along the width of the device demonstrates the importance of these parasitics (Isoplanar MOSFET, Width Cut).
The encroachment of the field implant into the channel not only narrows the channel width, but also increases the gate to bulk parasitic capacitance.
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Drawn width of the gate W |