Using JFET and MESFET Model Statements
Syntax
.MODEL mname NJF <LEVEL = val> <pname1 = val1> ...
.MODEL mname PJF <LEVEL = val> <pname1 = val1> ...
mname
|
Model name. Elements refer to the model by this name.
|
NJF
|
Identifies an N-channel JFET or MESFET model
|
LEVEL
|
The LEVEL parameter selects different DC model equations.
|
pname1=val1
|
Each JFET or MESFET model can include several model parameters.
|
PJF
|
Identifies a P-channel JFET or MESFET model
|
JFET and MESFET Model Parameters
DC characteristics are defined by the model parameters VTO and BETA. These parameters determine the variation of drain current with gate voltage. LAMBDA determines the output conductance, and IS, the saturation current, of the two gate junctions. Two ohmic resistances, RD and RS, are included. The charge storage is modeled by nonlinear depletion-layer capacitances for both gate junctions that vary as the -M power of junction voltage, and are defined by the parameters CGS, CGD, and PB.
Use parameters KF and AF to model noise, which is also a function of the series source and drain resistances (RS and RD), in addition to temperature. Use the parameters ALPHA and A to model MESFETs.
The AREA model parameter is common to both the element and model parameters. The AREA element parameter always overrides the AREA model parameter.
Table 17-3: JFET and MESFET Model Parameters
Model Parameters Common to All Levels
|
Geometric
|
ACM, ALIGN, AREA, HDIF, L, LDEL, LDIF, RD, RG, RS, RSH, RSHG, RSHL, W, WDEL
|
Capacitance
|
CAPOP, CGD, CGS, FC, M, PB, TT
|
Subthreshold
|
ND, NG
|
Noise
|
AF, KF
|
LEVEL=1 Model Parameters (JFET)
|
DC
|
BETA, IS, LAMBDA, N, VTO
|
LEVEL=2 Model Parameters (JFET)
|
DC
|
BETA, IS, LAMBDA, LAM1, N, VTO
|
LEVEL=3 Model Parameters (MESFET)
|
DC
|
ALPHA, BETA, D, GAMDS, IS, N, K1, LAMBDA, NCHAN, SAT, SATEXP, UCRIT, VBI, VGEXP, VP, VTO
|
The following subsections provide information about:
Gate Diode DC Parameters
Name (Alias)
|
Units
|
Default
|
Description
|
ACM
|
|
|
Area calculation method. This parameter allows the selection between the old SPICE unitless gate area calculations and the new Star-Hspice area calculations (see the ACM section). If W and L are specified, AREA becomes:
ACM=0 AREA=Weff/Leff
ACM=1 AREA=Weff · Leff
|
ALIGN
|
m
|
0
|
Misalignment of gate
|
AREA
|
|
|
Default area multiplier. This parameter affects the BETA, RD, RS, IS, CGS, and CGD model parameters.
AREAeff=M · AREA
Override this parameter using the element effective area.
|
HDIF
|
m
|
0
|
Distance of the heavily diffused or low resistance region from source or drain contact to lightly doped region
|
IS
|
amp
|
1.0e-14
|
Gate junction saturation current
ISeff = IS · AREAeff
|
L
|
m
|
0.0
|
Default length of FET. Override this parameter using the element L.
Leff = L · SCALM + LDELeff
|
LDEL
|
m
|
0.0
|
Difference between drawn and actual or optical device length
LDELeff = LDEL · SCALM
|
LDIF
|
m
|
0
|
Distance of the lightly doped region from heavily doped region to transistor edge
|
N
|
|
1.0
|
Emission coefficient for gate-drain and gate-source diodes
|
RD
|
ohm
|
0.0
|
Drain ohmic resistance (see the ACM section)
RDeff = RD /AREAeff, ACM=0
|
RG
|
ohm
|
0.0
|
Gate resistance (see the ACM section)
RGeff = RG · AREAeff, ACM=0
|
RS
|
ohm
|
0.0
|
Source ohmic resistance (see the ACM section)
RSeff = RS /AREAeff, ACM=0
|
RSH
|
ohm/sq
|
0
|
Heavily doped region, sheet resistance
|
RSHG
|
ohm/sq
|
0
|
Gate sheet resistance
|
RSHL
|
ohm/sq
|
0
|
Lightly doped region, sheet resistance
|
W
|
m
|
0.0
|
Default width of FET. Override this parameter using the element W.
Weff = W · SCALM + WDELeff
|
WDEL
|
m
|
0.0
|
Difference between drawn and actual or optical device width
WDELeff = WDEL · SCALM
|
Gate Capacitance LEVEL 1, 2, and 3 Parameters
Name (Alias)
|
Units
|
Default
|
Description
|
CAPOP
|
|
0.0
|
Capacitor model selector:
CAPOP=0 - default capacitance equation based on diode depletion layer
CAPOP=1 - symmetric capacitance equations (Statz)
CAPOP=2 - Avant! improvement to CAPOP=1
|
CALPHA
|
ALPHA
|
|
Saturation factor for capacitance model (CAPOP=2 only)
|
CAPDS
|
F
|
0
|
Drain to source capacitance for TriQuint model
CAPDSeff=CAPDS ·
|
CGAMDS
|
GAMDS
|
|
Threshold lowering factor for capacitance (CAPOP=2 only)
|
CGD
|
F
|
0.0
|
Zero-bias gate-drain junction capacitance
CGDeff = CGD · AREAeff
Override this parameter by specifying GCAP.
|
CGS
|
F
|
0.0
|
Zero-bias gate-source junction capacitance
CGSeff = CGS · AREAeff
Override this parameter by specifying GCAP
|
CRAT
|
|
0.666
|
Source fraction of gate capacitance (used with GCAP)
|
GCAP
|
F
|
|
Zero-bias gate capacitance. If specified,
CGSeff = GCAP · CRAT · AREAeff and
CGDeff = GCAP · (1-CRAT) · AREAeff
|
FC
|
|
0.5
|
Coefficient for forward-bias depletion capacitance formulas (CAPOP=0 and 2 only)
|
CVTO
|
VTO
|
|
Threshold voltage for capacitance model (CAPOP=2 only)
|
M (MJ)
|
|
0.50
|
Grading coefficient for gate-drain and gate-source diodes (CAPOP=0 and 2 only)
0.50 - step junction
0.33 - linear graded junction
|
PB
|
V
|
0.8
|
Gate junction potential
|
TT
|
s
|
0
|
Transit time
- option METHOD=GEAR is recommended when using transit time for JFET and MESFET
|
NOTE: Many DC parameters (such as VTO, GAMDS, ALPHA) can also affect capacitance.
DC Model LEVEL 1 Parameters
Name (Alias)
|
Units
|
Default
|
Description
|
LEVEL
|
|
1.0
|
LEVEL=1 invokes SPICE JFET model
|
BETA
|
amp/ V
2
|
1.0e-4
|
Transconductance parameter, gain
|
LAMBDA
|
1/V
|
0.0
|
Channel length modulation parameter
|
ND
|
1/V
|
0.0
|
Drain subthreshold factor (typical value=1)
|
NG
|
|
0.0
|
Gate subthreshold factor (typical value=1)
|
VTO
|
V
|
-2.0
|
Threshold voltage. If set, it overrides internal calculation. A negative VTO is a depletion transistor regardless of NJF or PJF. A positive VTO is always an enhancement transistor.
|
DC Model LEVEL 2 Parameters
Name (Alias)
|
Units
|
Default
|
Description
|
LEVEL
|
|
1.0
|
Level of FET DC model. LEVEL=2 is based on modifications to the SPICE model for gate modulation of LAMBDA.
|
BETA
|
amp /V
2
|
1.0e-4
|
Transconductance parameter, gain
|
LAMBDA
|
1/V
|
0.0
|
Channel length modulation parameter
|
LAM1
|
1/V
|
0.0
|
Channel length modulation gate voltage parameter
|
ND
|
1/V
|
0.0
|
Drain subthreshold factor (typical value=1)
|
NG
|
|
0.0
|
Gate subthreshold factor (typical value=1)
|
VTO
|
V
|
-2.0
|
Threshold voltage. When set, VTO overrides internal calculation. A negative VTO is a depletion transistor regardless of NJF or PJF. A positive VTO is always an enhancement transistor.
|
DC Model
LEVEL 3 Parameters
Name (Alias)
|
Units
|
Default
|
Description
|
LEVEL
|
|
1.0
|
Level of FET DC model. LEVEL=3 is the Curtice MESFET model.
|
A
|
m
|
0.5µ
|
Active layer thickness
Aeff = A · SCALM
|
ALPHA
|
1/V
|
2.0
|
Saturation factor
|
BETA
|
amp /V
2
|
1.0e-4
|
Transconductance parameter, gain
|
D
|
|
11.7
|
Semiconductor dielectric constant: Si=11.7, GaAs=10.9
|
DELTA
|
|
0
|
Ids feedback parameter of TriQuint model
|
GAMDS
(GAMMA
)
|
|
0
|
Drain voltage, induced threshold voltage lowering coefficient
|
LAMBDA
|
1/V
|
0.0
|
Channel length modulation parameter
|
K1
|
V
1/2
|
0.0
|
Threshold voltage sensitivity to bulk node
|
NCHAN
|
atom/cm
3
|
1.552e16
|
Effective dopant concentration in the channel
|
ND
|
1/V
|
0.0
|
Drain subthreshold factor
|
NG
|
|
0.0
|
Gate subthreshold factor (typical value=1)
|
SAT
|
|
0.0
|
Saturation factor
SAT=0 (standard Curtice model)
SAT= (Curtice model with hyperbolic tangent coefficient)
SAT=2 (cubic approximation of Curtice model (Statz))
|
SATEXP
|
|
3
|
Drain voltage exponent
|
UCRIT
|
V/cm
|
0
|
Critical field for mobility degradation
|
VBI
|
|
1.0
|
Gate diode built-in voltage
|
VGEXP (Q)
|
|
2.0
|
Gate voltage exponent
|
VP
|
|
|
Dinch-off voltage (default is calculated)
|
VTO
|
V
|
-2.0
|
Threshold voltage. If set, it overrides internal calculation. A negative VTO is a depletion transistor regardless of NJF or PJF. A positive VTO is always an enhancement transistor.
|
ACM (Area Calculation Method) Parameter Equations
The JFET model parameter ACM lets you select between the SPICE unitless gate area calculations and the Star-Hspice area calculations. The ACM=0 method (SPICE) uses the ratio of W/L to keep AREA unitless. The ACM=1 model (Star-Hspice) requires parameters such as IS, CGS, CGD, and BETA to have proper physics-based units.
In the following equations, lower case "m" indicates the element multiplier.
ACM=0
ACM=1
Or if RD=0,
or if RG=0,
or if RS=0,
Resulting calculations
NOTE: The model parameter units for IS, CGS, CGD, are unitless in ACM=0 and per square meter for ACM=1.
Example
j1 10 20 0 40 nj_acm0 w=10u l=1u
j2a 10 20 0 41 nj_acm1 w=10u l=1u
.model nj_acm0 njf LEVEL=3 capop=1 sat=3 acm=0
+ is=1e-14 cgs=1e-15 cgd=.3e-15
$$$ note different units for is,cgs,cgd
+ rs=100 rd=100 rg=5 beta=5e-4
+ vto=.3 n=1 ng=1.4 nd=1
+ k1=.2 vgexp=2 alpha=4 ucrit=1e-4 lambda=.1
+ satexp=2
+ eg=1.5 gap1=5e-4 gap2=200 d=13
.model nj_acm1 njf LEVEL=3 capop=1 sat=3 acm=1
+ is=1e-2 cgs=1e-3 cgd=.3e-3
$$$ note different units for is,cgs,cgd
+ rs=100 rd=100 rg=5 beta=5e-4
+ vto=.3 n=1 ng=1.4 nd=1
+ k1=.2 vgexp=2 alpha=4 ucrit=1e-4 lambda=.1
+ satexp=2
+ eg=1.5 gap1=5e-4 gap2=200 d=13
JFET and MESFET Capacitances
Gate Capacitance CAPOP=0
The DCAP option switch selects the diode forward bias capacitance equation:
DCAP=1
Reverse Bias:
vgd < FC · PB
vgs < FC · PB
Forward Bias:
DCAP=2 (Star-Hspice Default)
Reverse Bias:
vgd < 0
vgs < 0
Forward Bias:
DCAP=3
Limits peak depletion capacitance to FC · CGDeff or FC · CGSeff, with proper fall-off when forward bias exceeds PB (FC
>
1).
Gate Capacitance CAPOP=1
Gate capacitance CAPOP=1 is a charge conserving symmetric capacitor model most often used for MESFET model LEVEL 3.
where:
and:
CGD = High -vds Cgd at vgs = 0
CGS = High -vds Cgs at vgs = 0
CGD - CGDeff
CGS - CGSeff
Gate Capacitance CAPOP=2
The Statz capacitance equations
(See H. Statz, P.Newman, I.W.Smith, R.A. Pucel, and H.A. Haus, GaAs FET Device and Circuit Simulation in Spice) (CAPOP=1) contain mathematical behavior that has been found to be problematic when trying to fit data.
-
For vgs below the threshold voltage and Vds>0 (normal bias condition), Cgd is greater than Cgs and rises with Vds, while Cgs drops with Vds.
-
Although Cgd properly goes to a small constant representing a sidewall capacitance, Cgs drops asymptotically to zero with decreasing Vgs.
-
(For the behavior for Vds<0, interchange Cgs and Cgd and replace Vds with -Vds in the above descriptions.)
-
It can be difficult to simultaneously fit the DC characteristics and the gate capacitances (measured by S-parameters) with the parameters that are shared between the DC model and the capacitance model.
-
The capacitance model in the CAPOP=1 implementation also lacks a junction grading coefficient and an adjustable width for the Vgs transition to the threshold voltage. The width is fixed at 0.2.
-
Finally, an internal parameter for limiting forward gate voltage is set to 0.8 · PB in the CAPOP=1 implementation. This is not always consistent with a good fit.
The CAPOP=2 capacitance equations help to solve the problems described above.
CAPOP=2 Parameters
Parameter
|
Default
|
Description
|
CALPHA
|
ALPHA
|
Saturation factor for capacitance model
|
CGAMDS
|
GAMDS
|
Threshold lowering factor for capacitance
|
CVTO
|
VTO
|
Threshold voltage for capacitance model
|
FC
|
0.5
|
PB multiplier - typical value 0.9 gate diode limiting voltage=FC · PB.
|
M (MJ)
|
0.5
|
Junction grading coefficient
|
VDEL
|
0.2
|
Transition width for Vgs
|
Capacitance Comparison (CAPOP=1 and CAPOP=2)
CAPOP=1 vs. CAPOP=2. Cgs, Cgd vs. Vgs for Vds=0, 1, 2, 3, 4 and CAPOP=1 vs. CAPOP=2. Cgs, Cgd vs. Vds for Vgs=-1.5, -1.0, -0.5, 0 show comparisons of CAPOP=1 and CAPOP=2. Note in CAPOP=1 vs. CAPOP=2. Cgs, Cgd vs. Vgs for Vds=0, 1, 2, 3, 4 that below threshold (-0.6 v) Cgs for CAPOP=2 drops towards the same value as Cgd, while for CAPOP=1, CGS --> 0.
Note in CAPOP=1 vs. CAPOP=2. Cgs, Cgd vs. Vds for Vgs=-1.5, -1.0, -0.5, 0 how the Cgs-Cgd characteristic curve "flips over" below threshold for CAPOP=1, whereas for CAPOP=2, it is well-behaved.
JFET and MESFET DC Equations
DC Model Level 1
JFET DC characteristics are represented by the nonlinear current source, ids. The value of ids is determined by the equations:
vgst< 0 Channel pinched off
0<vgst<vds Saturated region
0<vds<vgst Linear region
The drain current at zero vgs bias (ids) is related to VTO and BETA by the equation:
At a given vgs, LAMBDA can be determined from a pair of drain current and drain voltage points measured in the saturation region where vgst<vds:
DC Model LEVEL 2
The DC characteristics of the JFET LEVEL 2 model are represented by the nonlinear current source (ids). The value of ids is determined by the equations:
vgst<0 Channel pinched off
Saturated region, forward bias
0<vgst<vds, vgs<0 Saturated region, reverse bias
0<vds<vgst Linear region
DC Model LEVEL 3
The DC characteristics of the MESFET LEVEL 3 model are represented by the nonlinear hyperbolic tangent current source (ids). The value of ids is determined by the equations:
vds>0 Forward region
If model parameters VP and VTO are not specified they are calculated as:
then,
vgst<0 Channel pinched off
vgst>0, SAT=0 On region
vgst>0, SAT=1 On region
vgst>0, SAT=2, vds<3/ALPHA On region
vgst>0, SAT=2, vds>3/ALPHA On region
If vgst >0, SAT=3 is the same as SAT=2, except exponent 3 and denominator 3 are parameterized as SATEXP, and exponent 2 of vgst is parameterized as VGEXP.
NOTE: idsubthreshold is a special function that calculates the subthreshold currents given the model parameters N0 and ND.
Star-Hspice Manual - Release 2001.2 - June 2001