Running the Two-Bit Adder Demo

This two-bit adder demonstrates many techniques to improve circuit simulation efficiency, accuracy, and productivity. The adder in demonstration file $installdir/demo/hspice/apps/mos2bit.sp is composed of two-input NAND gates defined by the subcircuit NAND. CMOS devices are parameterized with length, width, and output loading. Descriptive names enhance the readability of this circuit.

The subcircuit ONEBIT defines the two half adders with carry in and carry out. The two-bit adder is created by two calls to ONEBIT. Independent piecewise linear voltage sources provide input stimuli. Complex waveforms are created by the "R" repeat function.

 

Figure 31-1: One-bit Adder Subcircuit

 

Figure 31-2: Two-bit Adder Circuit

 

Figure 31-3: 1-bit NAND Gate Binary Adder

MOS Two-Bit Adder Input File

*FILE: MOS2BIT.SP - ADDER - 2 BIT ALL-NAND-GATE BINARY ADDER
.OPTIONS ACCT NOMOD FAST autostop scale=1u gmindc=100n
.param lmin=1.25  hi=2.8v lo=.4v vdd=4.5
.global vdd
.TRAN .5NS 60NS
.graph TRAN V(c[0]) V(carry-out_1) V(c[1]) V(carry-out_2) 
+ par('V(carry-in)/6 + 1.5') 
+ par('V(a[0])/6     + 2.0') 
+ par('V(b[0])/6     + 2.5') (0,5)
.MEAS PROP-DELAY TRIG V(carry-in) TD=10NS VAL='vdd*.5' RISE=1
+                TARG V(c[1])     TD=10NS VAL='vdd*.5' RISE=3
*
.MEAS PULSE-WIDTH  TRIG V(carry-out_1) VAL='vdd*.5' RISE=1
+                  TARG V(carry-out_1) VAL='vdd*.5' FALL=1
*
.MEAS FALL-TIME    TRIG V(c[1]) TD=32NS VAL='vdd*.9' FALL=1
+                  TARG V(c[1]) TD=32NS VAL='vdd*.1' FALL=1
VDD  vdd gnd DC vdd
X1    A[0]  B[0]  carry-in     C[0]  carry-out_1  ONEBIT
X2    A[1]  B[1]  carry-out_1  C[1]  carry-out_2  ONEBIT
Subcircuit Definitions
.subckt NAND  in1  in2  out   wp=10 wn=5
   M1  out  in1 vdd vdd P W=wp  L=lmin    ad=0
   M2  out  in2 vdd vdd P W=wp  L=lmin    ad=0
   M3  out  in1 mid gnd N W=wn  L=lmin    as=0
   M4  mid  in2 gnd gnd N W=wn  L=lmin    ad=0
   CLOAD out gnd 'wp*5.7f'
.ends
* switch model equivalent of the NAND. Gives a 10 times 
* speedup over the MOS version.
.subckt NANDx  in1  in2  out   wp=10 wn=5
   G1 out vdd vdd in1  LEVEL=1 MIN=1200 MAX=1MEG 1.MEG -.5MEG
   G2 out vdd vdd in2  LEVEL=1 MIN=1200 MAX=1MEG 1.MEG -.5MEG
   G3 out mid in1 gnd  LEVEL=1 MIN=1200 MAX=1MEG 1.MEG -.5MEG
   G4 mid gnd in2 gnd  LEVEL=1 MIN=1200 MAX=1MEG 1.MEG -.5MEG
   cout out gnd 300f
.ends
.subckt ONEBIT  in1  in2  carry-in  out  carry-out
		X1  in1      in2      #1_nand   NAND
		X2  in1      #1_nand  8         NAND
		X3  in2      #1_nand  9         NAND
		X4  8        9        10        NAND
		X5  carry-in 10       half1     NAND
		X6  carry-in half1    half2     NAND
		X7  10       half1    13        NAND
		X8  half2    13       out       NAND
		X9  half1    #1_nand  carry-out NAND
.ENDS ONEBIT
Stimuli
V1 carry-in gnd PWL(0NS,lo 1NS,hi 7.5NS,hi 8.5NS,lo 15NS lo R
V2 A[0] gnd PWL  (0NS,hi 1NS,lo 15.0NS,lo 16.0NS,hi 30NS hi R
V3 A[1] gnd PWL  (0NS,hi 1NS,lo 15.0NS,lo 16.0NS,hi 30NS hi R
V4 B[0] gnd PWL  (0NS,hi 1NS,lo 30.0NS,lo 31.0NS,hi 60NS hi
V5 B[1] gnd PWL  (0NS,hi 1NS,lo 30.0NS,lo 31.0NS,hi 60NS hi
Models
.MODEL N  NMOS LEVEL=3  VTO=0.7  UO=500    KAPPA=.25 KP=30U
+ ETA=.01    THETA=.04 VMAX=2E5 NSUB=9E16 TOX=400 GAMMA=1.5
+ PB=0.6     JS=.1M    XJ=0.5U  LD=0.1U   NFS=1E11 NSS=2E10
+ RSH=80     CJ=.3M    MJ=0.5   CJSW=.1N  MJSW=0.3
+ acm=2  capop=4
.MODEL P  PMOS LEVEL=3  VTO=-0.8 UO=150    KAPPA=.25 KP=15U
+ ETA=.015 THETA=.04 VMAX=5E4 NSUB=1.8E16 TOX=400 GAMMA=.672
+ PB=0.6    JS=.1M    XJ=0.5U  LD=0.15U    NFS=1E11  NSS=2E10
+ RSH=80    CJ=.3M    MJ=0.5   CJSW=.1N   MJSW=0.3
+ acm=2  capop=4
.END
Star-Hspice Manual - Release 2001.2 - June 2001