Scaling Buffer Strength

Sometimes there is a need to scale buffer strength (that is, increase or decrease current for output type buffers for a given value of the output voltage). This enables the same IBIS file to be used to simulate buffers of different strengths. Let us designate K as a factor for current multiplication. For the original buffer, the value of K=1. This section describes how to accomplish this scaling using the F-element for a single output buffer and differential output buffer.

The original circuit for a single output buffer is as follows:

Buffer nd_pu nd_pd nd_out nd_pc nd_gc

+ file=<filename> model=<modelname>

+ Rload nd_out gnd Rload_val

The scaled circuit for a single output buffer is as follows:

Buffer nd_pu nd_pd nd_out nd_pc nd_gc

+ file=<filename> model=<modelname>

+ Vsenser nd_out nd_out_prime V=0

+ Rload nd_out_prime gnd Rload_val

+ Felement gnd nd_out_prime Vsenser K-1

The original circuit for a differential output buffer is as follows:

Buffer1 nd_pu1 nd_pd1 nd_out1 nd_pc1 nd_gc1

+ file=<filename1> model=<modelname1>

Buffer2 nd_pu2 nd_pd2 nd_out2 nd_pc2 nd_gc2

+ file=<filename2> model=<modelname2>

+ R_load n_out1 n_out2 R_load_value

The scaled circuit for a differential output buffer is as follows:

Buffer1 nd_pu1 nd_pd1 nd_out1 nd_pc1 nd_gc1

+ file=<filename1> model=<modelname1>

Buffer2 nd_pu2 nd_pd2 nd_out2 nd_pc2 nd_gc2

+ file=<filename2> model=<modelname2>

+ V_sense n_out1 n_out1_prime 0V

+ F_element n_out2 n_out1_prime v_sense K-1

+ R_load n_out1_prime n_out2 R_load_value

Please note the polarity of the F-element. For the scaling factor K=1, the current controlled current source does not supply any current and effectively we have the original circuit.

Buffers in subcircuits

**********************************************

* example 1 * buffers in subcircuit, power=on

**********************************************

v_in1 nd_in1 0 pulse

+ ( 0V 1.0V CLK_Q_PRD DLT_TIME DLT_TIME CLK_H_PRD CLK_PRD )

v_en1 nd_en1 0 1V

v_in2 nd_in2 0 pulse

+ ( 1.1V 0V CLK_Q_PRD DLT_TIME DLT_TIME CLK_H_PRD CLK_PRD )

v_en2 nd_en2 0 1V

x1 nd_out1 nd_in1 nd_en1 nd_outofin1 buffer11

x2 nd_out2 nd_in2 nd_en2 nd_outofin2 buffer11

R_load nd_out1 nd_out2 50

.subckt buffer11 nd_out0 nd_in0 nd_en0 nd_outofin0

b_io_0 nd_pu0 nd_pd0 nd_out nd_in0 nd_en0 nd_outofin0 nd_pc0 nd_gc0

+ file = '92lv090b.ibs'

+ model = 'DS92LV090A_DOUT'

+ typ=typ power=on

+ buffer=3

+ interpol=1

+ xpin nd_out nd_out0 pin22

.ends

.subckt pin22 nd_out nd_out0

R_pin nd_out_c nd_out0 50m

C_pin nd_out_c 0 0.3p

L_pin nd_out nd_out_c 2n

.ends

In this example buffers are connected to power sources implicitly by Hspice inside subcircuit. Subcircuit external terminals does not need to include nd_pu, nd_pd, nd_pc, nd_gc.

**********************************************

* example 2* buffers in subcircuit, power=off

**********************************************

v_in1 nd_in1 0 pulse

+ ( 0V 1.0V CLK_Q_PRD DLT_TIME DLT_TIME CLK_H_PRD CLK_PRD )

v_en1 nd_en1 0 1V

v_in2 nd_in2 0 pulse

+ ( 1.1V 0V CLK_Q_PRD DLT_TIME DLT_TIME CLK_H_PRD CLK_PRD )

v_en2 nd_en2 0 1V

x1 nd_power 0 nd_out1 nd_in1 nd_en1 nd_outofin1 nd_power 0 buffer11

x2 nd_power 0 nd_out2 nd_in2 nd_en2 nd_outofin2 nd_power 0 buffer11

R_load nd_out1 nd_out2 50

.subckt buffer11 nd_pu0 nd_pd0 nd_out0 nd_in0 nd_en0 nd_outofin0 nd_pc0 nd_gc0

r_0 nd_pu0 nd_pd0 1.23456789x

b_io_0 nd_pu0 nd_pd0 nd_out nd_in0 nd_en0 nd_outofin0 nd_pc0 nd_gc0

+ file = '92lv090b.ibs'

+ model = 'DS92LV090A_DOUT'

+ typ=typ power=off

+ buffer=3

+ interpol=1

+ xpin nd_out nd_out0 pin22

.ends

.subckt pin22 nd_out nd_out0

R_pin nd_out_c nd_out0 50m

C_pin nd_out_c 0 0.3p

L_pin nd_out nd_out_c 2n

.ends

V_power nd_power 0 3.3V

In this example, only one voltage source, V_power, is used to power all buffers. All power nodes, nd_pu, nd_pd, nd_pc, nd_gc, should be explicitly provided.