There are two methods of using digital stimuli in a Star-Hspice input netlist: U Element digital input files and vector input files. They are both described in this section.
The U Element can reference digital input and digital output models for mixed mode simulation. Viewlogic's Viewsim mixed mode simulator uses Star-Hspice with digital input from Viewsim. The state information comes from a digital file if Star-Hspice is being run in standalone mode. Digital outputs are handled in a similar fashion. In digital input file mode, the input file is <design>.d2a and the output file is named <design>.a2d.
A2D and D2A functions accept the terminal "\" backslash character as a line-continuation character to allow more than 255 characters in a line. This is needed because the first line of a digital file, which contains the signal name list, is often longer than the maximum line length accepted by some text editors.
A digital D2A file must not have a blank first line. If the first line of a digital file is blank, Star-Hspice issues an error message.
The following example demonstrates the use of the "\" line continuation character to format an input file for text editing. The file contains a signal list for a 64-bit bus.
...
a00 a01 a02 a03 a04 a05 a06 a07 \
a08 a09 a10 a11 a12 a13 a14 a15 \
... * Continuation of signal names
a56 a57 a58 a59 a60 a61 a62 a63 * End of signal names
... * Remainder of file
The general syntax for including a U Element digital source in a Star-Hspice netlist is:
General form:
Uxxx interface nlo nhi mname SIGNAME = sname IS = val
Model Syntax:
.MODEL mname U LEVEL=5 <parameters...>
The following example shows the usage of the U Element and model as a digital input for a Star-Hspice netlist.
* EXAMPLE OF U-ELEMENT DIGITAL INPUT
UC carry-in VLD2A VHD2A D2A SIGNAME=1 IS=0
VLO VLD2A GND DC 0
VHI VHD2A GND DC 1
.MODEL D2A U LEVEL=5 TIMESTEP=1NS,
+ S0NAME=0 S0TSW=1NS S0RLO = 15, S0RHI = 10K,
+ S2NAME=x S2TSW=3NS S2RLO = 1K, S2RHI = 1K
+ S3NAME=z S3TSW=5NS S3RLO = 1MEG,S3RHI = 1MEG
+ S4NAME=1 S4TSW=1NS S4RLO = 10K, S4RHI = 60
.PRINT V(carry-in)
.TRAN 1N 100N
.END
where the associated digital input file is:
1
00 1:1
09 z:1
10 0:1
11 z:1
20 1:1
30 0:1
39 x:1
40 1:1
41 x:1
50 0:1
60 1:1
70 0:1
80 1:1
The general syntax for including a digital output in a Star-Hspice output is:
General form:
U<name> interface reference mname SIGNAME = sname
Model Syntax:
.MODEL mname U LEVEL=4 <parameters...>
* EXAMPLE OF U-ELEMENT DIGITAL OUTPUT
VOUT carry_out GND PWL 0N 0V 10N 0V 11N 5V 19N 5V 20N 0V
+ 30N 0V 31N 5V 39N 5V 40N 0V
VREF REF GND DC 0.0V
UCO carry-out REF A2D SIGNAME=12
* DEFAULT DIGITAL OUTPUT MODEL (no "X" value)
.MODEL A2D U LEVEL=4 TIMESTEP=0.1NS TIMESCALE=1
+ S0NAME=0 S0VLO=-1 S0VHI= 2.7
+ S4NAME=1 S4VLO= 1.4 S4VHI=9.0
+ CLOAD=0.05pf
.TRAN 1N 50N
.END
and the digital output file should look like:
12
0 0:1
105 1:1
197 0:1
305 1:1
397 0:1
where the "12" represents the signal name, the first column is the time in units of 0.1 nanoseconds, and the second column has the signal value:name pairs. Subsequent outputs would be represented in the same file by more columns.
The following two-bit MOS adder uses the digital input file. In the following plot, nodes `A[0], A[1], B[0], B[1], and CARRY-IN' all come from a digital file input (see Digital File Signal Correspondence). SPICE outputs a digital file.
FILE: MOS2BIT.SP - ADDER - 2 BIT ALL-NAND-GATE BINARY ADDER
*
.OPTIONS ACCT NOMOD FAST scale=1u gmindc=100n post
.param lmin=1.25 hi=2.8v lo=.4v vdd=4.5
.global vdd
*
.TRAN .5NS 60NS
.MEAS PROP-DELAY TRIG V(carry-in) TD=10NS VAL='vdd*.5' RISE=1
+ TARG V(c[1]) TD=10NS VAL='vdd*.5' RISE=3
*
.MEAS PULSE-WIDTH TRIG V(carry-out_1) VAL='vdd*.5' RISE=1
+ TARG V(carry-out_1) VAL='vdd*.5' FALL=1
*
.MEAS FALL-TIME TRIG V(c[1]) TD=32NS VAL='vdd*.9' FALL=1
+ TARG V(c[1]) TD=32NS VAL='vdd*.1' FALL=1
*
VDD vdd gnd DC vdd
X1 A[0] B[0] carry-in C[0] carry-out_1 ONEBIT
X2 A[1] B[1] carry-out_1 C[1] carry-out_2 ONEBIT
*
* Subcircuit Definitions
.subckt NAND in1 in2 out wp=10 wn=5
M1 out in1 vdd vdd P W=wp L=lmin ad=0
M2 out in2 vdd vdd P W=wp L=lmin ad=0
M3 out in1 mid gnd N W=wn L=lmin as=0
M4 mid in2 gnd gnd N W=wn L=lmin ad=0
CLOAD out gnd `wp*5.7f'
.ends
*
.subckt ONEBIT in1 in2 carry-in out carry-out
X1 in1 in2 #1_nand NAND
X2 in1 #1_nand 8 NAND
X3 in2 #1_nand 9 NAND
X4 8 9 10 NAND
X5 carry-in 10 half1 NAND
X6 carry-in half1 half2 NAND
X7 10 half1 13 NAND
X8 half2 13 out NAND
X9 half1 #1_nand carry-out NAND
.ENDS ONEBIT
*
* Stimulus
UC carry-in VLD2A VHD2A D2A SIGNAME=1 IS=0
UA[0] A[0] VLD2A VHD2A D2A SIGNAME=2 IS=1
UA[1] A[1] VLD2A VHD2A D2A SIGNAME=3 IS=1
UB[0] B[0] VLD2A VHD2A D2A SIGNAME=4 IS=1
UB[1] B[1] VLD2A VHD2A D2A SIGNAME=5 IS=1
*
uc0 c[0] vrefa2d a2d signame=10
uc1 c[1] vrefa2d a2d signame=11
uco carry-out_2 vrefa2d a2d signame=12
uci carry-in vrefa2d a2d signame=13
*
* Models
.MODEL N NMOS LEVEL=3 VTO=0.7 UO=500 KAPPA=.25 KP=30U
+ ETA=.01 THETA=.04 VMAX=2E5 NSUB=9E16 TOX=400 GAMMA=1.5
+ PB=0.6 JS=.1M XJ=0.5U LD=0.1U NFS=1E11 NSS=2E10
+ RSH=80 CJ=.3M MJ=0.5 CJSW=.1N MJSW=0.3
+ acm=2 capop=4
*
.MODEL P PMOS LEVEL=3 VTO=-0.8 UO=150 KAPPA=.25 KP=15U
+ ETA=.015 THETA=.04 VMAX=5E4 NSUB=1.8E16 TOX=400 GAMMA=.672
+ PB=0.6 JS=.1M XJ=0.5U LD=0.15U NFS=1E11 NSS=2E10
+ RSH=80 CJ=.3M MJ=0.5 CJSW=.1N MJSW=0.3
+ acm=2 capop=4
*
* Default Digital Input Interface Model
.MODEL D2A U LEVEL=5 TIMESTEP=0.1NS,
+ S0NAME=0 S0TSW=1NS S0RLO = 15, S0RHI = 10K,
+ S2NAME=x S2TSW=5NS S2RLO = 1K, S2RHI = 1K
+ S3NAME=z S3TSW=5NS S3RLO = 1MEG,S3RHI = 1MEG
+ S4NAME=1 S4TSW=1NS S4RLO = 10K, S4RHI = 60
VLD2A VLD2A 0 DC lo
VHD2A VHD2A 0 DC hi
*
* Default Digital Output Model (no "X" value)
.MODEL A2D U LEVEL=4 TIMESTEP=0.1NS TIMESCALE=1
+ S0NAME=0 S0VLO=-1 S0VHI= 2.7
+ S4NAME=1 S4VLO= 1.4 S4VHI=6.0
+ CLOAD=0.05pf
VREFA2D VREFA2D 0 DC 0.0V
.END
The digital vector file consists of three parts:
To incorporate this information into your simulation, you need to include this line in your netlist:
The Vector Pattern Definition section defines the vectors -- their names, sizes, signal direction, and so on -- and must occur first in the digital vector file. A sample Vector Pattern Definition section follows:
radix 1111 1111
vname a b c d e f g h
io iiii iiii
tunit ns
Keywords such as radix , vname are explained in the "Defining Tabular Data" section later in this chapter.
The Waveform Characteristics section defines various attributes for signals, such as the rise or fall time, thresholds for logic `high' or `low', and so on. A sample Waveform Characteristics section follows:
trise 0.3 137F 0000
tfall 0.5 137F 0000
vih 5.0 137F 0000
vil 0.0 137F 0000
The Tabular Data section defines the values of the input signals at specified times. The time is listed in the first column, followed by signal values, in the order specified by the vname statement.
An example of tabular data follows:
11.0 1000 1000
20.0 1100 1100
33.0 1010 1001
A line beginning with a semi-colon ";" is considered a comment line. Comments may also start at any point along a line. Star-Hspice ignores characters following a semi-colon.
; This is a comment line
radix 1 1 4 1234 ; This is a radix line
Like netlists, a line beginning with a plus sign "+" is a continuation from the previous line.
An example of a vector pattern definition follows:
; specifies # of bits associated with each vector
radix 1 2 444
;****************************************************
; defines name for each vector. For multi-bit
; vectors, innermost [] provide the bit index range,
; MSB:LSB
vname v1 va[[1:0]] vb[12:1]
;actual signal names: v1, va[0], va[1], vb1 ... vb12
;****************************************************
; defines vector as input, output, or bi-direc
io i o bbb
; defines time unit
tunit ns
;****************************************************
; vb12-vb5 are output when `v1' is `high'
enable v1 0 0 FF0
; vb4-vb1 are output when `v1' is `low'
enable ~v1 0 0 00F
;****************************************************
; all signals have delay of 1 ns
; Note: do not put unit (e.g., ns) again here because
; this value will be multiplied by the unit specified
; in the `tunit' line.
tdelay 1.0
; signals va1 and va0 have delays of 1.5ns
tdelay 1.5 0 3 000
;****************************************************
; specify input rise and fall times (if you want
; different rise and fall times, use trise/
; tfallstmt.)
; Note: do not put unit (e.g., ns) again here because
; this value will be multiplied by the unit specified
; in the `tunit' line.
slope 1.2
;****************************************************
; specify the logic `high' voltage for input signals
vih 3.3 1 0 000
vih 5.0 0 0 FFF
; likewise, may specify logic `low' with `vil'
;****************************************************
; va & vb switch from `lo' to `hi' at 1.75 volts
vth 1.75 0 1 FFF
;****************************************************
; tabular data section
10.0 1 3 FFF
20.0 0 2 AFF
30.0 1 0 888
.
.
.
Although this section generally appears last in a digital vector file, following the Vector Pattern and Waveform Characteristics definitions, we describe it first to introduce the definitions of a vector .
The Tabular Data section defines (in tabular format) the values of the signals at specified times. Its general format is:
time1 signal1_value1 signal2_value1 signal3_value1...
time2 signal1_value2 signal2_value2 signal3_value2...
time3 signal1_value3 signal2_value3 signal3_value3...
The set of values for a particular signal over all times is a vector , a vertical column in the tabular data and vector table. Thus, the set of all signal1_value x constitute one vector. Signal values may have the legal states described in the following section.
Rows in the tabular data section must appear in chronological order because row placement carries sequential timing information.
10.0 1000 0000
15.0 1100 1100
20.0 1010 1001
30.0 1001 1111
This example feature eight signals and therefore eight vectors. The first signal (starting from the left) has a vector [1 1 1 1]; the second has a vector [0 1 0 0]; and so on.
Star-Hspice converts each input signal into a PWL (piecewise linear) voltage source and a series resistance. The legal states for an input signal are:
For the 0, 1, X, x, U, u states, the resistance value is set to zero; for the L, H states, the resistance value is defined by the out (or outz ) statement; and for the Z, z states, the resistance value is defined by the triz statement.
Star-Hspice converts each output signal into a .DOUT statement in the netlist. During simulation, Star-Hspice compares the actual results with the expected output vector(s), and if the states are different, an error message appears. The legal states for expected outputs include:
|
Expect HIGH IMPEDANCE (don't care) Z, z are treated as "don't care" because Star-Hspice cannot detect a high impedance state. |
...
; start of tabular section data
11.0 1 0 0 1
20.0 1 1 0 0
30.0 1 0 0 0
35.0 x x 0 0
Star-Hspice also accepts Verilog sized format for number specification:
<size> '<base format> <number>
The <size> specifies (in decimal) the number of bits, and <base format> indicates binary ('b or 'B), octal ('o or 'O), or hexadecimal ('h or 'H). Valid <number> fields are combinations of the characters 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Depending on the <base format> chosen, only a subset of these characters may be legal.
You may also use unknown values (X) and high impedance (Z) in the <number> field. An X or Z sets four bits in the hexadecimal base, three bits in the octal base, and one bit in the binary base.
If the most significant bit of a number is 0, X, or Z, the number is automatically extended (if necessary) to fill the remaining bits with (respectively) 0, X, or Z. If the most significant bit is 1, it is extended with 0.
Here we specify values for: a 4-bit signal in binary, a 12-bit signal in hexadecimal, a 32-bit signal in binary, and an 8-bit signal in hexadecimal.
Equivalents of these lines in non-Verilog format would be:
1111
AB xxxx
ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ
1000 0000
Very often tabular data is periodic, so it is unnecessary to specify the absolute time at every time point. When a user specifies the period statement, the tabular data section omits the absolute times (see Using Tabular Data for details).
radix 1111 1111
vname a b c d e f g h
io iiii iiii
tunit ns
period 10
; start of vector data section
1000 1000
1100 1100
1010 1001
The Vector Pattern Definition section defines the sequence or order for each vector stimulus, as well as any individual characteristics. The statements in this section (except the radix statement) might appear in any order, and all keywords are case-insensitive.
The radix statement specifies the number of bits associated with each vector. Valid values for the number of bits range from 1 to 4.
Only one radix statement must appear in the file, and it must be the first noncomment line.
This example illustrates two 1-bit signals followed by a 4-bit signal, followed by a 1-bit, 2-bit, 3-bit, 4-bit signals, and finally eight 1-bit signals.
; start of vector pattern definition section
radix 1 1 4 1234 1111 1111
The vname statement defines the name of each vector. If not specified, a default name will be given to each signal: V1, V2, V3, and so on. If you define more than one vname statement, the last one overrules the previous one.
radix 1 1 1 1 1 1 1 1 1 1 1 1
vname V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12
Provide the range of the bit indices with a square bracket [] and a colon syntax:
[ starting_index : ending index ]
The vname name is required for each bit, and a single name may be associated with multiple bits ( such as bus notation).
The bit order is MSB:LSB. This bus notation syntax may also be nested inside other grouping symbols such as <>, (), [], etc. The name of each bit will be vname with the index suffix appended.
radix 2 4
vname VA[0:1] VB[4:1]
the resulting names of the voltage sources generated are:
where VA0 and VB4 are the MSBs and VA1 and VB1 are the LSBs.
the resulting names of the voltage sources are:
VA[0] VA[1] VB<4> VB<3> VB<2> VB<1>
This example shows how to specify a single bit of a bus:
This example generates signals A0, A1, A2, ... A23:
The io statement defines the type of each vector. The line starts with a keyword io and followed by a string of i, b, o, or u definitions indicating whether each corresponding vector is an input, bidirectional, output, or unused vector, respectively.
If the io statement is not specified, all signals are assumed input signals. If you define more than one io statements, the last one overrules previous ones.
The tunit statement defines the time unit in the digital vector file for period , tdelay , slope , trise , tfall , and absolute time . It must be:
If you do not specify the tunit statement, the default time unit value is ns . If you define more than one tunit statement, the last one will overrule the previous one.
The tunit statement in this example specifies that the absolute times in the tabular data section are 11.0ns, 20.0ns, and 33.0ns, respectively.
tunit ns
11.0 1000 1000
20.0 1100 1100
33.0 1010 1001
The period statement defines the time interval for the tabular data section so that specifying the absolute time at every time point is not necessary. Thus, if a period statement is provided alone (without the tskip statement), the tabular data section contains only signal values, not absolute times. The time unit of period is defined by the tunit statement.
In this example, the first row of the tabular data (1000 1000) is for time 0ns. The second row of the tabular data (1100 1100) is for time 10ns. The third row of the tabular data (1010 1001) is for time 20ns.
radix 1111 1111
period 10
1000 1000
1100 1100
1010 1001
The tskip statement specifies that the absolute time field in the tabular data is to be ignored. In this way, the absolute time field of each row may be kept in the tabular data (but ignored) when using the period statement.
radix 1111 1111
period 10
tskip
11.0 1000 1000
20.0 1100 1100
33.0 1010 1001
the absolute times 11.0, 20.0 and 33.0 are ignored.
The enable statement specifies the controlling signal(s) of bidirectional signals and is absolutely required for all bidirectional signals. If more than one enable statement exists, the last value will overrule the previous ones, and a warning message will be issued.
The syntax is a keyword enable, followed by the controlling signal name and the mask that defines the (bidirectional) signals to which enable applies.
The controlling signal of bi-directional signals must be an input signal with radix of 1. The bidirectional signals become output when the controlling signal is at state 1 (or high). If you wish to reverse this default control logic, you must start the control signal name with `~'.
In this example, signals x and y are bidirectional, as defined by the `b' in the io line. The first enable statement indicates that x (as defined by the position of `F') becomes output when signal a is 1. The second enable specifies that bidirectional bus y becomes output when signal a is 0.
radix 144
io ibb
vname a x[3:0] y[3:0]
enable a 0 F 0
enable ~a 0 0 F
This section describes how to modify the waveform characteristics of your circuit.
The tdelay , idelay and odelay statements define the delay time of the signal relative to the absolute time of each row in the tabular data section; idelay applies to the input signals, odelay applies to the output signals, while tdelay applies to both input and output signals.
The statement starts with a keyword tdelay (or idelay , odelay ) followed by a delay value, and then followed by a mask, which defines the signals to which the delay will be applied. If you do not provide a mask, the delay value will be applied to all the signals.
The time unit of tdelay , idelay and odelay is defined by the tunit statement. Normally, you only need to use the tdelay statement; only use the idelay and odelay statements to specify different input and output delay times for bi-directional signals. idelay settings on output signals (or odelay settings on input signals) are ignored with warning message issued.
More than one tdelay ( idelay , odelay ) statement can be specified. If more than one tdelay ( idelay , odelay ) statement is applied to a signal, the last value will overrule the previous ones, and a warning will be given. If you do not specify the signal delays by a tdelay ( idelay or odelay ) statement, Star-Hspice defaults to zero.
The first tdelay statement indicates that all signals have the same delay time 1.0. The delay time of some signals are overruled by the subsequent tdelay statements. The V2 and Vx signals have delay time -1.2, and V4 V5[0:1] V6[0:2] have a delay of 1.5. The V7[0:3] signals have an input delay time of 2.0 and an output delay time of 3.0.
radix 1 1 4 1234 11111111
io i i o iiib iiiiiiii
vname V1 V2 VX[3:0] V4 V5[1:0] V6[0:2] V7[0:3]
+V8 V9 V10 V11 V12 V13 V14 V15
tdelay 1.0
tdelay -1.2 0 1 1 0000 00000000
tdelay 1.5 0 0 0 1370 00000000
idelay 2.0 0 0 0 000F 00000000
odelay 3.0 0 0 0 000F 00000000
The slope statement specifies input signal rise/fall time, with the time unit defined by the tunit statement. You can specify the signals to which the slope applies using a mask. If the slope statement is not provided, the default slope value is 0.1 ns.
If you specify more than one slope statement, the last value will overrule the previous ones, and a warning message will be issued. The slope statement has no effect on the expected output signals. The rising time and falling time of a signal will be overruled if trise and tfall are specified.
The first example indicates that the rising and falling times of all signals are 1.2 ns, whereas the second specifies a rising/falling time of 1.1 ns for the first, second, sixth, and seventh signal.
The trise statement specifies the rise time of each input signal (for which the mask applies). The time unit of trise is defined by the tunit statement.
If you do not specify the rising time of the signals by any trise statement, the value defined by the slope statement is used. If you apply more than one trise statements to a signal, the last value will overrule the previous ones, and a warning message will be issued.
trise 0.3
trise 0.5 0 1 1 137F 00000000
trise 0.8 0 0 0 0000 11110000
The trise statements have no effect on the expected output signals.
The tfall statement specifies the falling time of each input signal (for which the mask applies). The time unit of tfall is defined by the tunit statement.
If you do not specify the falling time of the signals by a tfall statement, Star-Hspice uses the value defined by the slope statement. If you specify more than one tfall statement to a signal, the last value will overrule the previous ones, and a warning message will be issued.
tfall 0.5
tfall 0.3 0 1 1 137F 00000000
tfall 0.9 0 0 0 0000 11110000
The tfall statements have no effect on the expected output signals.
The keywords out and outz are equivalent and specify the output resistance of each signal (for which the mask applies); out (or outz ) applies to the input signals only.
If you do not specify the output resistance of a signal by an out (or outz ) statement, Star-Hspice uses the default (zero). If you specify more than one out (or outz ) statement to a signal, Star-Hspice overrules the last value with the previous ones, and issues a warning message.
out 15.1
out 150 1 1 1 0000 00000000
outz 50.5 0 0 0 137F 00000000
The out (or outz ) statements have no effect on the expected output signals.
The triz statement specifies the output impedance when the signal (for which the mask applies) is in tristate ; triz applies to the input signals only.
If you do not specify the tristate impedance of a signal by a triz statement, Star-Hspice assumes 1000M. If you apply more than one triz statement to a signal, the last value will overrule the previous ones, and Star-Hspice will issue a warning.
triz 15.1M
triz 150M 1 1 1 0000 00000000
triz 50.5M 0 0 0 137F 00000000
The triz statements have no effect on the expected output signals.
The vih statement specifies the logic high voltage of each input signal to which the mask applies.
If you specify the logic high voltage of the signals by a vih statement, Star-Hspice assumes 3.3. If you apply more than one vih statements to a signal, the last value will overrule the previous ones, and Star-Hspice will issue a warning.
vih 5.0
vih 5.0 1 1 1 137F 00000000
vih 3.5 0 0 0 0000 11111111
The vih statements have no effect on the expected output signals.
The vil statement specifies the logic low voltage of each input signal to which the mask applies.
If you specify the logic low voltage of the signals by a vil statement, Star-Hspice assumes 0.0. If you apply more than one vil statement to a signal, the last value will overrule the previous ones, and Star-Hspice will issue a warning.
vil 0.0
vil 0.0 1 1 1 137F 11111111
The vil statements have no effect on the expected output signals.
Similar to the tdelay statement, the vref statement specifies the name of the reference voltage for each input vector to which the mask applies; vref applies to the input signals only.
vname v1 v2 v3 v4 v5[1:0] v6[2:0] v7[0:3] v8 v9 v10
vref 0
vref 0 111 137F 000
vref vss 0 0 0 0000 111
When Star-Hspice implements it into the netlist, the voltage source realizes v1 :
as will v2 , v3 , v4 , v5 , v6 , and v7 . However, v8 will be realized by
If you do not specify the reference voltage name of the signals by a vref statement, Star-Hspice assumes 0. If you apply more than one vref statement, the last value will overrule the previous ones, and Star-Hspice issues a warning. The vref statements have no effect on the output signals.
Similar to the tdelay statement, the vth statement specifies the logic threshold voltage of each signals to which the mask applies; vth applies to the output signals only. The threshold voltage is used to decide the logic state of Star-Hspice's output signals for comparison with the expected output signals.
If you do not specify the threshold voltage of the signals by a vth statement, Star-Hspice assumes 1.65. If you apply more than one vth statements to a signal, the last value will overrule the previous ones, and Star-Hspice issues a warning.
vth 1.75
vth 2.5 1 1 1 137F 00000000
vth 1.75 0 0 0 0000 11111111
The vth statements have no effect on the input signals.
The voh statement specifies the logic high voltage of each output signal to which the mask applies.
If you do not specify the logic high voltage by a voh statement, Star-Hspice assumes 3.3. If you apply more than one voh statements to a signal, the last value will overrule the previous ones, and Star-Hspice issues a warning.
voh 4.75
voh 4.5 1 1 1 137F 00000000
voh 3.5 0 0 0 0000 11111111
The voh statements have no effect on input signals.
The vol statement specifies the logic low voltage of each output signal to which the mask applies.
If you do not specify the logic low voltage by a vol statement, Star-Hspice assumes 0.0. If you apply more than one vol statements to a signal, the last value will overrule the previous ones, and Star-Hspice issues a warning.
vol 0.5
vol 0.5 1 1 1 137F 11111111
The vol statements have no effect on input signals.