This section describes the buffers as implemented in Star-Hspice. Please refer to Specifying Common Keywords for details on using keywords shown in the syntax examples in the following sections.
The syntax of an input buffer element card is:
B_INPUT nd_pc nd_gc nd_in nd_out_of_in
+ file='filename' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={1|input}]
+ [interpol={1|2}]
+ [nowarn]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
where the total number of external nodes is equal to 4.
If keyword power=on (default) is specified, nodes nd_pc and nd_gc are connected to voltage sources with values taken from the IBIS file. You should not connect these nodes to voltage sources. However, names for these nodes should be provided, so you can print out the voltage values if required. For example:
.PRINT V(nd_pc) V(nd_gc)
If keyword power=off is specified, Star-Hspice does not connect these nodes to voltage sources. You should connect the nodes to voltage sources either directly or through an RLC network, or a transmission line.
There are no special rules for node_in and node_in can connect to I, E, F, G, and H elements. The buffer measures and processes the voltage on this node and sends a response to node nd_out_of_in. The node nd_out_of_in is connected to the voltage source as shown in Figure Input Buffer. It is an error to connect this node to a voltage source. If power=off, nodes nd_pc, nd_gc can be connected to the ground is the intention is to specify voltage zero on these nodes.
V_out_of_in is a digital signal that assumes values of either 0 or 1 depending on the voltages V_in, Vinh, Vinl, and Polarity. Star-Hspice processes V_out_of_in according to the following rules.
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Initially V_out_of_in is set to 0 if V_in < (Vinh+Vinl)/2 and to 1 in the opposite case. |
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Initially V_out_of_in is set to 0 if V_in > (Vinh+Vinl)/2 and to 1 in the opposite case |
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Input Buffer shows a single circuit specified on a single element card. V_out_of_in is a voltage source whose value is a function of V_in (as well as of thresholds Vinl, Vinh, and parameter Polarity). It can be used to drive other circuits.
If pc_scal or gc_scal arguments exist and pc_scal_value or gc_scal_value do not equal 1.0, then PC or GC iv curve will be adjusted using the pc_scal_value or gc_scal_value.
The syntax for an output buffer element card is:
B_OUTPUT nd_pu nd_pd nd_out nd_in [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={2|output}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pd=c_com_pd_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 4 or 6, any other number is an error. If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will simply add Power_Clamp and/or Ground_Clamp I-V curves data to corresponding Pull_Up and/or Pull_Down
I-V curves data.
However, the optional nodes nd_pc and nd_gc are needed if:
If optional nodes nd_pc and nd_gc are needed, but omitted from the element card, Star-Hspice issues a warning and connects nd_pc to nd_pu and nd_gc to nd_pd.
If keyword power=on (default) is specified, nodes nd_pu, nd_pd, and if specified, nd_pc and nd_gc, are connected to voltage sources with values taken from the IBIS file. You should not connect these nodes to voltage sources. However, names for these nodes should be provided, so you can print out the voltage values if required. For example:
.PRINT V(nd_pu) V(nd_pd)
If keyword power=off is specified , Star-Hspice does not connect these nodes to voltage sources. You should connect the nodes to voltage sources either directly or through an RLC network or a transmission line.
There are no special rules for node nd_out. The voltage on this node is controlled by the digital signal on the node nd_in. Now any voltage source, current source, voltage controlled voltage source, voltage controlled current source, current controlled voltage source, or current controlled current source can be connected to the nd_in as shown in the following example:
V_in nd_in gnd 0V pulse( 0V 1V 1n 0.1n 0.1n 7.5n 15n )]
If power=off, nodes nd_pu, nd_pd, nd_pc, nd_gc can be connected to the ground if the intention is to have zero voltage on these nodes.
V_in is a controlling signal representing a digital signal with values 0 and 1. However, Star-Hspice will take any signal and process according to the following rules:
If pc_scal (or gc_scal, pu_scal, pd_scal) argument exists and pc_scal_value (or gc_scal_value, pu_scal_value, pd_scal_value) does not equal to 1.0, the PC (or GC, PU, PD) iv curve will be adjusted using the pc_scal_value (or gc_scal_value, pu_scal_value, pd_scal_value).
If rwf_scal (or fwf_scal) argument exists and rwf_scal_value (or fwf_scal_value) does not equal to 1.0, rising and falling vt curves will be adjusted using rwf_scal_value (or fwf_scal_value).
If spu_scal (or spd_scal) argument exists and spu_scal_value (or spd_scal_value) does not equal to 0.0, but at the same time power is equal to off and (spu_scal_value-spd_scal_value) does not equal to the corresponding value in the .ibs file, then the iv curves of PU (or PD) will be adjusted using spu_scal_value (or spd_scal_value).
The syntax for a tristate buffer element card is:
B_3STATE nd_pu nd_pd nd_out nd_in nd_en [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={4|three_state}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pd=c_com_pd_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 5 or 7; any other number is an error. If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will simply add Power_Clamp and/or Ground_Clamp I-V curves data to corresponding Pull_Up and/or Pull_Down I-V curves data.
However, the optional nodes nd_pc and nd_gc are needed if:
If optional nodes nd_pc and nd_gc are needed, but omitted from the element card, Star-Hspice issues a warning and connects nd_pc to nd_pu and nd_gc to nd_pd.
If keyword power=on (default) is specified, nodes nd_pu, nd_pd, and if specified, nd_pc and nd_gc are connected to voltage sources with values taken from the IBIS file. You should not connect these nodes to voltage sources.
However, names for these nodes should be provided in the netlist, so you can print out the voltage values if required. For example:
.PRINT V(nd_pu) V(nd_pd)
If keyword power=off is specified, Star-Hspice does not connect these nodes to voltage sources. You should connect the nodes to voltage sources either directly or through an RLC network, or a transmission line.
There are no special rules for nd_out. The voltage on this node is controlled by the digital signal on the nodes nd_in, nd_en. Voltage sources must be connected to the nodes
nd_in
,
nd_en
V_in nd_in gnd 0V pulse( 0V 1V 1n 0.1n 0.1n 7.5n 15n )
V_en nd_en gnd 0V pulse( 0V 1V 3n 0.1n 0.1n 7.5n 15n ) ].
Nodes nd_pu, nd_pd, nd_pc, and nd_gc can be connected to the ground if the intention is to have zero voltage on these nodes. Nodes nd_in, nd_en can not be connected to the ground.
V_in and V_en are controlling signals representing digital signals with values 0 and 1. Star-Hspice will take any signal and process according to the following rules:
The syntax of an input/output buffer element card is:
B_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={3|input_output}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pd=c_com_pd_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 6 or 8; any other number is an error. If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will simply add Power_Clamp and/or Ground_Clamp I-V curves data to corresponding Pull_Up and/or Pull_Down I-V curves data.
However, the optional nodes nd_pc and nd_gc are needed if:
If optional nodes nd_pc and nd_gc are needed, but omitted from the element card, Star-Hspice issues a warning and connects nd_pc to nd_pu and nd_gc to nd_pd.
If keyword power=on (default) is specified, nodes nd_pu and nd_pd, and if specified, nd_pc and nd_gc, are connected to voltage sources with values taken from the IBIS file. You should not connect these nodes to voltage sources. However, names for these nodes should be provided in the netlist, so you can print out the voltage values if required. For example:
.PRINT V(nd_pu) V(nd_pd)
If keyword power=off is specified, Star-Hspice does not connect these nodes to voltage sources. You should connect the nodes to voltage sources either directly or through an RLC network or a transmission line.
There are no special rules for node nd_out. The voltage on this node is controlled by the digital signal on the nodes nd_in, nd_en. Voltage sources must be connected to the nodes nd_in, nd_en as shown in the following example:
V_in nd_in gnd 0V pulse (0V 1V 1n 0.1n 0.1n 7.5n 15n)
V_en nd_en gnd 0V pulse (0V 1V 3n 0.1n 0.1n 7.5n 15n).
Nodes nd_pu, nd_pd, nd_pc, and nd_gc can be connected to the ground if the intention is to have zero voltage on these nodes.
The node nd_out_of_in is connected to a voltage source (see Input-Output Buffer). It is an error to connect this node to a voltage source or the ground.
The input-output buffer is a combination of the tristate buffer and the input buffer. See Input Buffer and Tristate Buffer for more information.
The input-output buffer can function as an input buffer. In this case, the resultant digital signal V_out_of_in on the node nd_out_of_in is controlled by the voltage V_out on the node nd_out.
For the input buffer, this controlling voltage is called V_in and any corresponding node is nd_in.
The input-output buffer uses V_in, nd_in notations to denote the controlling voltage and controlling input node for the output part of the buffer.
If the input-output buffer is not in the DISABLE state (this includes ENABLE state and transitions to ENABLE->DISABLE and DISABLE->ENABLE), then it functions as a tristate buffer. If input-output buffer is in the DISABLE state, it functions as an input buffer.
However, there is a difference in the digital output of the input part of the buffer (voltage V_out_of_in ). Because V_out_of_in is not always defined (e.g. the buffer is in ENABLE state, or Vinl < V_out < Vinh at the time moment, when the transition to DISABLE state is completed) and because we want to preserve logical LEVELs 0 and 1 for LOW and HIGH states, V_out_of_in takes the value 0.5 when it is undefined.
Input-Output Buffer shows a single circuit specified on a single element card. The V_out_of_in is a voltage source whose value is a function of V_out (as well as of thresholds Vinl, Vinh and parameter Polarity). It can be used to drive other circuits.
Open drain and open sink buffers do not have pullup circuitry. Open source buffers do not have pulldown circuitry. However, the element cards for these three buffers coincide with the element card for the output buffer. Accordingly, you should always specify names for pullup and pulldown nodes, nd_pu and nd_pd , even if the buffer does not have pullup or pulldown circuitry.
All rules given in Output Buffer apply to open drain, open sink, and open source buffers with the following exceptions:
I/O open drain and I/O open sink buffers do not have pullup circuitry. I/O open source buffers do not have pulldown circuitry. However, the element cards for these three buffers coincide with the element card for the input-output buffer. Accordingly, you should always specify names for pullup and pulldown nodes, nd_pu and nd_pd , even if the buffer does not have pullup or pulldown circuitry.
All rules given in Input/Output Buffer are applicable to I/O open drain, I/O open sink, and I/O open source buffers with the following exceptions:
The syntax of the input ECL buffer element card is:
B_INPUT_ECL nd_pc nd_gc nd_in nd_out_of_in
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={11|input_ecl}]
+ [interpol={1|2}]
+ [nowarn]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
The input ECL buffer is similar to the input buffer. The only difference is in default values for Vinl and Vinh .
The syntax of the output ECL buffer element card is:
B_OUTPUT_ECL nd_pu nd_out nd_in [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={12|output_ecl}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 3 or 5, any other number is an error. The output ECL buffer does not have a pulldown node. The pulldown table in the IBIS file is referenced in respect to pullup voltage.
If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will issue an error message (this simulator behavior is different from that for the output buffer).
In other respects, the output ECL buffer is similar to the output buffer. Please see Output Buffer for more information.
The syntax for the tristate ECL buffer element card is:
B_3STATE_ECL nd_pu nd_out nd_in nd_en [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={14|three_state_ecl}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 4 or 6, any other number is an error. The tristate ECL buffer does not have a pulldown node. The pulldown table in the IBIS file is referenced in respect to pullup voltage.
If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will issue an error message (this simulator behavior is different from that for the tristate buffer).
In other respects, the tristate ECL buffer is similar to the tristate buffer. Please see Tristate Buffer for more information.
The syntax for the input-output ECL buffer element card is:
B_IO_ECL nd_pu nd_out nd_in nd_en nd_out_of_in [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={13|io_ecl}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={0|1|2}] [ramp_rwf={0|1|2}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]
Nodes nd_pc and nd_gc are optional. However, either both or none can be specified. The total number of external nodes is either 5 or 7, any other number is an error. The tristate ECL buffer does not have a pulldown node. The pulldown table in the IBIS file is referenced in respect to pullup voltage.
If nodes nd_pc and nd_gc are not given on the element card but Power_Clamp and/or Ground_Clamp I-V curves are present in the model in question, then the simulator will issue an error message (this simulator behavior is different from that for Input-Output buffer).
In other respects, the input-output ECL buffer is similar to the input-output buffer. Please see Input/Output Buffer for more information.
