Optimizing TDR Packaging

Packaging plays an important role in determining the overall speed, cost, and reliability of a system. With today's small feature sizes and high levels of integration, a significant portion of the total delay comes from the time required for a signal to travel between chips.

Multilayer ceramic technology has proven to be well suited for high-speed GaAs IC packages.

The multichip module minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuity between the chips mounted on the substrate with a more direct path (die-bump-interconnect-bump-die), thus eliminating wirebonding. In addition, narrower and shorter wires on the ceramic substrate have much less capacitance and inductance than the PC board interconnections.

Time domain reflectometry (TDR) is the closest measurement to actual digital component function. It provides a transient display of the impedance versus time for pulse behavior.

With a digitized TDR file, you can automatically select design components using the Star-Hspice optimizer. You can extract critical points from digitized TDR files using the Star-Hspice .MEASURE statement, and use the results as electrical specifications for optimization. This process eliminates recurring design cycles to find component values to curve-fit the TDR files.

 

Figure 25-3: Optimization Process

 

Figure 25-4: General Method for TDR Optimization

The following is a method used for realistic high-speed testing of packaging.

Test fixtures were designed that closely emulate a high-speed system environment. A Star-Hspice model was constructed for measurements using ideal transmission lines and discrete components.

The circuit tested contained the following components:

 

Figure 25-5: SPICE Model for Package-Plus-Test Fixture
Optimized Parameters: XTD, CSMA, LPIN, and LPK

The package tests performed traditional time domain measurements using a digital sampling oscilloscope. Tests were designed to observe the reflected and transmitted signals derived from the built-in high-speed pulse generator and translated output signals into digitized time domain reflectometer files (voltage vs. time).

A fully developed SPICE model was used to simulate the package-plus-test fixture. The simulated and measured reflected/transmitted signals were compared.

The input netlist file for this experiment is shown on the following pages. Output plots are shown in Figures Reflected Signals Before Optimization through Transmitted Signals after Optimization.

You can further investigate this experiment using Star-Hspice's advanced lossy transmission lines to include attenuation and dispersion.

TDR Optimization Procedure

Measure Critical Points in the TDR Files
	Vin 1 0 PWL(TIME,VOLT)
	.DATA D_TDR
	    TIME    VOLT
	    0       0.5003mV
	    0.1n    0.6900mV
	     ...
	    2.0n    6.4758mV
	.ENDDATA
	.TRAN DATA=D_TDR
	.MEAS .....
	.END
Set Up an Input Optimization File
$ SPICE MODEL FOR PACKAGE-PLUS-TEST FIXTURE
$ AUTHOR: DAVID H. SMITH & RAJ M. SAVARA
.OPTION POST RELV=1E-4 RELVAR=1E-2 
$ DEFINE PARAMETERS
.PARAM LV=-0.05 HV=0.01 TD=1P TR=25P TF=50P TPW=10N TPER=15N
$ PARAMETERS TO BE OPTIMIZED
.PARAM CSMA=OPT1(500f,90f,900f,5f) 
+      XTD=OPT1(150p,100p,200p)
+      LPIN=OPT1(0.65n,0.10n,0.90n,0.2n) 
+      LPK=OPT1(1.5n,0.75n,3.0n,0.2n) 
+      LPKCL=0.33n
+      LPKV=0.25n
Signal Generator
VIN   S1 GND PULSE LV HV TD TR TF TPW TPER
RIN   S1 S2  50
CIN1  S2 GND 250f
TCOAX S2 GND SIG_OUT GND ZO=50 TD=50p
ETF Board
CSNAL SIG_OUT GND CSMA
TEFT2 SIG_OUT GND E3 GND ZO=50 TD=XTD
RLOSS1 E3 E4 10
CRPAD1 E4 GND 200f
TLIN2 E4 GND ETF_OUT GND ZO=50 TD=35p
CPAD2 ETF_OUT GND 300f
TLIN1 E5 GND E6 GND ZO=50 TD=35p
CPAD1 E5 GND 300f
CRPAD2 E6 GND 200f
RLOS1 E6 E7 10
TEFT1 E7 GND E8 GND ZO=50 TD=XTD
CSMA2 E8 GND CSMA
TCOAX2 E8 GND VREF1 GND ZO=50 TD=50p
RIN1 VREF1 GND 50
Package Body
LPIN1 ETF_OUT P1 LPIN
LPK1 GND P5 LPK
LPKGCL P5 NVOUT2 LPKCL
CPKG1 P1 P5 250f
LPKV1 P1 P2 LPKV
TPKGL P2 NVOUT2 VOUT NVOUT2 ZO=65 TD=65P
CBPL VOUT NVOUT 1f
ROUT1 VOUT NVOUT 50meg
LPIN2 E5 P3 LPIN
CPKG2 P3 NVOUT2 250f
LPKV2 P3 P4 LPKV
TPKG2 P4 NVOUT2 VOUT2 NVOUT2 ZO=65 TD=65p
CBPD1 VOUT2 NVOUT2 1f
ROUT2 VOUT2 NVOUT2 50meg
$ BEFORE OPTIMIZATION
.TRAN .004NS 2NS
$ OPTIMIZATION SETUP
.MODEL OPTMOD OPT ITROPT=30
.TRAN .05NS 2NS SWEEP OPTIMIZE=OPT1 
+                RESULTS=MAXV,MINV,MAX_2,COMP1,PT1,PT2,PT3
+                MODEL=OPTMOD
$ MEASURE CRITICAL POINTS IN THE REFLECTED SIGNAL
$ GOALS ARE SELECTED FROM MEASURED TDR FILES
.MEAS TRAN COMP1 MIN V(S2) FROM=100p TO=500p GOAL=-27.753 
.MEAS TRAN PT1 FIND V(S2) AT=750p GOAL=-3.9345E-3 WEIGHT=5
.MEAS TRAN PT2 FIND V(S2) AT=775p GOAL=2.1743E-3 WEIGHT=5
.MEAS TRAN PT3 FIND V(S2) AT=800p GOAL=5.0630E-3 WEIGHT=5
$ MEASURE CRITICAL POINTS IN THE TRANSMITTED SIGNAL
$ GOALS ARE SELECTED FROM MEASURED TDR FILES
.MEAS TRAN MAXV FIND V(VREF1)AT=5.88E-10 GOAL=6.3171E-
+ WEIGHT=7
.MEAS TRAN MINV FIND V(VREF1) AT=7.60E-10 GOAL=-9.9181E-3 
.MEAS TRAN MAX_2 FIND V(VREF1) AT=9.68E-10 GOAL=4.9994E-3
$ COMPARE SIMULATED RESULTS WITH MEASURED TDR VALUES
.TRAN .004NS 2NS
.PRINT C_REF=V(S2) C_TRAN=V(VREF1)
.END

 

Figure 25-6: Reflected Signals Before Optimization
Figure 25-7: Reflected Signals After Optimization

 

Figure 25-8: Transmitted Signals Before Optimization

 

Figure 25-9: Transmitted Signals after Optimization
Star-Hspice Manual - Release 2001.2 - June 2001