Index -- All Volumes
$installdir installation directory
3-50
A2D
output model parameters
5-54
absolute
AC
circuit and pole/zero models
29-47
output
small signal analysis
9-38
accessing customer support
vi
ACCURACY
accuracy
adder
admittance
ALFA, .FFT parameter
28-8
algebraic
algorithms
Damped Pseudo Transient algorithm
10-48
Levenberg-Marquardt
13-53
local
ALPHA model parameter
14-19
.ALTER
alternate saturation
model parameters
AM
modulation frequency
28-13
AMI gate capacitance model
20-94
AMP model parameter
26-66
analog
behavioral
circuit simulation of a digital system
25-4
Analog Artist interface
9-11
Analysis
analysis
example
modulator/demodulator
28-16
MOSFETs
example
active low-pass filter
27-15
CMOS differential amplifier
27-12
high-pass Butterworth filter
27-10
RC network
transfer function (.TF)
26-46
area
JFETs and MESFETs
AREA capacitor parameter
15-6
ASIC
ASPEC
asterisk comment delimiter
3-9
asymptotic waveform evaluation
29-2
ATEM characterization system
3-50
ATLEN model parameter
C-36
automatic model selection
multisweep or .TEMP effect
D-4
AV1K model parameter
26-67
AvanLink
DA
Mentor Graphics products
B-8
AvanWaves waveform display
B-7
,
B-12
AVD model parameter
26-67
average value, measuring
8-46
AWE
See
asymptotic waveform evaluation
B# node name in CSOS
3-19
backslash continuation character
3-3
,
7-8
BART FFT analysis keyword
28-8
base
collector capacitance
16-36
resistance equations
16-32
base-collector junction
16-5
base-emitter
capacitance equations
16-34
basic model parameters
MOSFETs
behavioral
amplitude modulator
26-62
BJTs
phase detector model
26-97
double-edge triggered flip-flop
26-36
elements
phase detector model
26-88
silicon controlled rectifier
26-59
Berkeley
NonQuasi-Static (NQS) model
22-23
BiCMOS
bidirectional circuits, wire RC model
14-2
binary
bisection
BISECTION model parameter
30-7
BJTs
base
width modulation model parameters
16-9
base-collector
depletion capacitance equations
16-37
diffusion capacitance equations
16-36
base-emitter
depletion capacitance equations
16-35
diffusion capacitance equations
16-34
beta
capacitance temperature equations
16-46
current
models
element template listings
8-59
energy gap temperature equations
16-42
excess phase equation
16-39
high current Beta degradation parameters
16-10
junction capacitance
LEVEL 2
temperature equations
16-49
LEVEL 8 HiCUM
low current Beta degradation parameters
16-9
models
parasitic capacitance
16-6
parasitics
capacitance model parameters
16-12
resistance model parameters
16-10
resistor temperature equations
16-49
quasi-saturation model
16-50
S-parameters, optimization
13-60
subcircuits, scaled
16-55
substrate
capacitance equations
16-39
temperature
capacitance equations
16-46
compensation equations
16-42
saturation equations
16-44
variable base resistance equations
16-32
BLACK FFT analysis keyword
28-8
Blackman-Harris FFT analysis window
28-4
,
28-28
branch current
breakpoint table
BRIEF
Broyden update data, printing
9-8
VERSION parameter effects
21-111
BSIM2 LEVEL 39 model
3-31
VERSION parameter effects
21-193
BSIM3 model
BSIM3 SOI FD
BSIM3 Version 2 MOS model
22-2
BSIM3v3 model
ECL
open
bulk
semiconductor devices
17-2
transconductance, MOSFETs
20-23
BULK wire model parameters
14-4
Butterworth filter pole/zero analysis
27-10
BV diode model parameter
15-4
Cadence
Analog Artist
See
Artist, Analog Artist
Composer, with AvanLink
B-2
capacitance
CAPOP model selector
20-7
diode, Fowler-Nordheim
15-49
distribution for wire RC model
14-2
equations
junction, internal collector
16-37
manufacturing variations
13-24
MOSFETs
MOSFETs
capacitance-voltage plots, generating
9-28
,
10-23
capacitor
conductance requirement
10-47
DC sweep evaluation
16-34
device
equation selector option
15-5
parameters
temperature, equations
14-8
CAPL model parameter
C-36
CASMOS
CBD model parameter
20-27
CBS model parameter
20-27
CCCS
CDB model parameter
20-28
CENDIF optimization parameter
13-41
channel length modulation, MOSFETs
equations
parameters
characteristic impedance
C-73
characterization of models
10-14
charge conservation
20-91
circuits
design
nonplanar and planar technologies
20-15
transient responses
29-46
RC
simulating
with Signetics drivers
25-18
CJA model parameter
20-28
CJBR model parameter
15-36
CJGATE model parameter
20-28
CJGR model parameter
15-36
CJP model parameter
20-28
CJSR model parameter
15-36
CJSW model parameter
20-28
CLEN model parameter
C-36
CLOAD model parameter
5-54
clock
CLOSE optimization parameter
13-41
CMI
function calling protocol
23-36
CMI_AssignInstanceParm
23-23
CMI_AssignModelParm
23-22
CMOS
differential amplifier, pole/zero analysis
27-12
tristate buffer, optimization
13-55
CMRR
coax
coefficients
collector-substrate junction
16-5
column laminated data
3-28
comlinear device models
D-10
commands
comment line (digital vector files)
5-62
common
model interface (CMI)
23-1
Common Simulation Data Format
9-11
comparators
complex poles and zeros
29-30
compression of input files
3-2
computer platforms for HSpice
1-6
concatenated data files
3-26
conductance
continuation character, parameter strings
7-8
continuation of line (digital vector file)
5-62
control characters in input
3-3
algorithm selection
10-22
DC operating point analysis
10-22
transient analysis
conventions
source-drain reversal conventions
23-43
convergence
increasing iterations
10-23
autoconverge process
10-42
floating point overflow
10-48
operating point Debug mode
10-7
core
coupled line noise simulation example
25-27
CPU time
CSB model parameter
20-28
CUR element parameter
26-18
current
ABSMOS floor value for convergence
9-22
,
10-41
controlled
element template listings
8-57
element template listings
8-57
convention
in HSPICE elements
8-23
-??
operating point table
10-6
CUT optimization parameter
13-42
D2A
input model parameters
5-51
Dallas Semiconductor model
20-5
Damped Pseudo Transient algorithm
10-48
data
driven
PWL source function
files, disabling printout
9-6
,
9-8
sampler, behavioral
26-63
data-driven analysis
3-21
DC
capacitor conductances
10-47
convergence control options
10-22
equations
operating point
initial conditions file
3-54
parameters
JFETs
sensitivity analysis
10-19
small-signal analysis
10-20
external data with .DATA
3-22
JFETs and MESFETs
overriding in BJTs models
16-3
JFETs and MESFETs capacitance
17-6
DEF model parameter
26-68
DEFAULT_INCLUDE variable
3-54
with multiple .ALTER statements
3-42
DELAY
delays
problems and solutions
25-3
DELEN model parameter
C-36
ideal delay elements
11-26
oscillator circuits
11-26
DELTA
DELVTO model parameter
13-9
demo files
2n2222 BJTs transistor characterization
31-32
2n3330 JFETs transistor characterization
31-32
AC
A/D flash converter
31-30
adders
72-transistor two-bit
31-28
BJT NAND gate two-bit
31-27
NAND gate four-bit binary
31-26
air core transformer
31-35
algebraic
amplitude modulator
31-27
automatic model selection program
31-36
voltage to frequency converter
31-26
bisection
BJTs
BSIM3 model, LEVEL=47
31-35
capacitances, MOS models
charge conservation, MOS models
CMOS
differential amplifier
31-26
coax transmission line
31-39
current controlled
DC analysis, MOS model LEVEL=34
31-36
differential amplifier
31-26
edge triggered flip-flop
31-27
FFT
Blackman-Harris window
31-34
data-driven transient analysis
31-34
harmonic distortion
31-33
high frequency detection
31-33
intermodulation distortion
31-34
modulated pulse source
31-34
Monte Carlo, Gaussian distribution
31-34
product of waveforms
31-34
single-frequency FM source
31-34
small-signal distortion
31-33
fifth-order
elliptical switched capacitor
31-28
fourth-order Butterworth
31-35
matching lossy to ideal
31-30
switched capacitor low-pass
31-27
gamma model LEVEL=6
31-36
impact ionization plot
31-36
IRF340 NMOS transistor characterization
31-32
I-V
and C-V plots, LEVEL=3
31-36
plots
MOSFETs model LEVEL=13
31-36
SOSFET's model LEVEL=27
31-36
junction tunnel diode
31-29
lumped
magnetic core transformer
31-35
Monte Carlo
Gaussian distribution
31-27
uniform distribution
31-27
MOS
NMOS E-mode model, LEVEL=8
31-38
2n3947 Gummel model
31-33
diode
GaAs
PCI
Monte Carlo analysis
31-36
worst-case modeling
31-36
phase
photolithographic effects
31-27
piecewise linear source
GaAs differential amplifier
31-38
NMOS
RC circuit optimization
31-30
resistor temperature coefficients
31-30
Royer magnetic core oscillator
31-35
series source coupled transmission lines
31-39
setup
shunt terminated transmission lines
31-39
silicon controlled rectifier
31-28
single-frequency FM source
31-38
SNAP to HSPICE conversion
31-29
temperature effects
total radiation dose
31-37
transistor characterization
31-32
twinlead transmission line model
31-39
unity gain frequency
31-29
Viewsim
voltage
controlled
to frequency converter
31-26
worst case skew model
31-27
depletion
capacitance
derivative, measuring
8-43
design
high speed, problems and solutions
25-3
Design Architect
Design Viewpoint Editor (DVE)
device
capacitor, equations
14-10
inductor, equations
14-17
dialectric
dielectric
thickness, wire model parameters
14-5
differentiator, behavioral
26-55
diffusion
capacitance equations
15-26
layer process parameters, MOSFETs LEVEL 13
21-106
DIFSIZ optimization parameters
13-42
digital
DIM2
DIM3
diodes
depletion capacitance
15-26
diffusion capacitance
15-26
convergence problems
15-5
elements
Fowler-Nordheim diodes
15-49
capacitance parameters (table)
15-12
DC parameters (table)
15-9
metal model capacitance parameters (table)
15-13
noise parameters (table)
15-13
capacitance equations
20-46
nongeometric junction
15-3
poly model capacitance parameters (table)
15-13
polysilicon capacitor length
4-13
scaling
series resistance units
15-11
temperature
compensation equations
15-28
equations
grading coefficient
15-32
junction capacitance
15-31
directories
installation directory
3-50
Discrete Fourier Transform
28-1
distortion
DLAT model parameter
20-30
DNB model parameter
20-28
documentation
dollar sign ($) comment delimiter
3-9
drain current equation, MOSFETs LEVEL 47
22-15
drain-to-source current, convergence error tolerance
9-20
,
10-37
DTA model parameter
15-35
DTEMP
DV
DVDT
dynamic timestep algorithm
11-34
controlling voltage
26-14
data
sampler application
26-63
element
integrator application
26-54
polynomial
temperature coefficients
26-13
transformer application
26-57
E elements
ECL
effective capacitance
effective channel length, MOSFETs
equations
parameters
effective channel width, MOSFETs
equations
parameters
effective mobility
MOSFETs, equations
parameters, LEVEL 6
21-75
electrical measurements
ELEMENT
element
active
checking, suppression of
9-8
markers, mutual inductors
4-10
parameters
See
element parameters
4-1
passive
statement, current output
8-22
transconductance
voltage gain
current-controlled
independent
saturable core
voltage-controlled
ELEMENT parameters
element parameters
data driven PWL function
5-18
mutual inductors, Kxxx
4-9
PWL
transmission lines
element statements
elements
templates
enable (digital vector file)
5-72
encryption
Encryption structure example
E-13
Encryption, 8-byte key
E-9
.END statement
for multiple HSPICE runs
3-45
energy gap temperature equations
environment variables
EPFL-EKV MOSFETs model
22-85
epitaxial
equations
BJTs
parasitic resistor temperature
16-49
capacitance
DC
device
diodes
Frohman-Bentchkowski
21-77
inductor
MOSFET models
MOSFETs
channel length modulation
20-111
models
IDS
surface potential temperature
20-109
resistor
temperature
variable
names and constants
17-11
wire
equivalent
circuit
variables and constants
20-20
ERR1
errors
bulk node not specified
14-7
cannot open
digital file has blank first line
5-50
environment variables
A-6
internal timestep too small
9-34
,
9-39
,
9-46
,
9-48
,
10-5
,
10-25
,
10-53
,
11-3
,
11-12
,
11-13
,
11-23
missing .END statement
3-2
negative slope for magnetization level
14-19
no DC path to ground
10-47
parameter name conflict
8-38
reference to undefined inductor
14-18
special characters in input
3-3
system resource inaccessible
8-18
timestep control error in transmission lines
C-61
tolerances
optimization by bisection
30-8
EXA model parameter
20-28
example
AC analysis
Hspice vs. SPICE methods
8-31
capacitance, MOSFETs
20-64
.DATA
Hspice vs .SPICE methods
.MODEL CARDS NMOS model
22-53
MOSFETs
network analysis, bipolar transistor
12-21
parameter extraction
14-24
transient analysis
EXD model parameter
20-28
EXJ model parameter
20-28
EXP model parameter
20-28
EXP source function
fall time
rise time
experimental methods
exponential
expressions
EXS model parameter
20-28
EXTRAPOLATION
controlling voltage
26-30
polynomial
temperature coefficients
26-29
F elements
fall time
FAQ
environment variables
A-6
Fast Fourier Transform
FFT
analysis
alfa control parameter
28-8
example
modulator/demodulator
28-16
frequency
harmonic distortion
28-16
field effect transistor
20-16
field programmable gate arrays
25-22
field solver
file descriptors limit
8-18
files
AC analysis
concatenated data files
3-26
DC analysis
multiple simulation runs
3-45
output
subcircuit node cross-listing
3-57
transient analysis
filing a documentation bug
iv
filters
30 degree phase shift
29-17
pole/zero analysis
floating point overflow
FMAX
FORMAT .FFT parameter
28-7
Fourier
transfer function H(f)
29-5
FREQ
function
transconductance element statement
29-8
voltage gain element statement
29-9
frequency
domain to time domain
29-1
domain, transfer function
29-20
low model parameters
16-5
Frequency Table Model
6-4
frequency-domain model
6-2
Frohman-Bentchkowski equations
21-77
FROM
FS
functions
amplitude modulator application
26-62
element value multiplier
26-20
maximum
minimum
parameter value multiplier
29-11
polynomial
temperature coefficients
26-20
tunnel diode application
26-58
voltage to resistance factor
26-20
G elements
GaAsFET model DC optimization
13-67
gate
charge sharing coefficient
20-72
MOSFETs
parameters
temperature equations, JFETs and MESFETs
17-42
GAUSS
FFT analysis
parameter distribution
13-14
GBW model parameter
26-69
geometric model parameter
16-6
geometry
JFETs and MESFETs parameters
17-7
MOSFETs model parameters
20-30
transistor field effect
20-16
getting customer support
vi
global
JFETs and MESFETs conductance
17-6
golden parser (IBIS)
19-1
maximum version number
8-11
GRAD optimization parameter
13-42
gradient data, printing
9-8
GRAMP
graph data
ground
plane, transmission lines
C-5
GSCAL
Gxxx element parameters
26-18
controlling voltage
26-25
element
polynomial
temperature coefficients
26-25
H elements
HAMM FFT analysis keyword
28-8
HANN FFT analysis keyword
28-8
HARRIS FFT analysis keyword
28-8
HD2
HD3
HDIF model parameter
20-30
HiCUM model
BJT
hierarchical designs, flattened
3-6
HSPICE
ground for transmission lines
C-18
installation directory
3-50
version
Hspice junction diode model
22-24
hybrid (H) parameters
8-29
hysteresis, Jiles-Atherton example
14-23
IBIS
keywords
limitations/restrictions
19-5
IBOS model parameter
26-70
IC
balancing input nodes
26-66
ideal
idelay (digital vector file)
5-73
IDS
Cypress depletion model
20-6
equations
LEVEL 5
LEVEL 6
LEVEL 8
imaginary
vs. real component ratio
10-32
imaginary vs. real component ratio
9-36
impact ionization
impulse response h(t)
29-5
inactive devices
.inc file encryption
E-12
independent sources
current
element template listings
8-58
data driven PWL function
5-18
source value parameter
5-3
elements
voltage
element template listings
8-57
individual element temperature
13-5
temperature equation
14-17
inductors
device
temperature, equation
14-17
saved operating point
10-11
input
data
concatenated data files
3-26
deleting library data
3-43
external, with .DATA statement
3-22
filenames on networks
3-29
for data driven analysis
3-21
files
unprintable characters
3-3
netlist
.END statement requirement
3-45
sections and chapter references
3-7
input/output
open
installation
installation directory $installdir
3-50
insulation breakdown devices
15-48
integration
integrator, behavioral
26-53
Intel PCI Speedway models
D-15
interconnect
interfaces
intermodulation distortion
12-9
internal
INTERPOLATION
intrinsic model parameters
inverse Laplace transform
29-33
inverter
ion-implanted devices
20-3
ISC model parameter
26-70
isoplanar
MOSFETs
silicon gate transistor
20-17
ISPICE LEVEL 6 model
21-72
iterations
ITL1
ITROPT optimization parameter
13-42
I-V and C-V plotting demo
31-7
Jacobian data, printing
9-8
JFETs
capacitance
CAPOP=2 model parameters
17-29
DC
model
element
gate
model
n-channel specification
17-13
noise
p-channel specification
17-13
temperature
TOM model parameters
17-46
Jiles-Atherton
example
parameter extraction
14-24
JIS model parameter
26-70
JSDBR model parameter
15-35
JSDGR model parameter
15-36
JSDSR model parameter
15-35
JSGBR model parameter
15-35
JSGSR model parameter
15-35
JSW model parameter
20-27
Juncap diode
electrical variable
15-39
Juncap diodes
JUNCAP model parameters
22-62
junction
capacitor parameters
16-11
diodes
model
parameters
MOSFETs LEVELs 49 and 53
22-44
setting
Junction diode
KAISER FFT analysis keyword
28-8
Kerwin's circuit, pole/zero analysis
27-8
keywords
.AC statement parameters
12-5
analysis statement syntax
13-39
DATA statement parameters
3-21
.DC statement parameters
10-15
.FFT statement parameters
28-7
.MEASUREMENT statement parameters
8-47
.MODEL statement parameters
8-12
optimization syntax
13-38
.TRAN statement parameters
11-5
Kirchhoff's Current Law (KCL) test
9-21
,
10-26
L capacitor parameter
15-6
LAPLACE
transconductance element statement
29-6
voltage gain element statement
29-6
Laplace
frequency
POLE (pole/zero) function
29-28
LATD model parameter
20-30
latent devices
Lattin-Jenkins-Grove model
20-5
layer stacks, transmission line
18-37
LC oscillator model
26-83
LDIF model parameter
20-30
LENGTH model parameter
13-22
LEVEL
model
optimization parameter
13-42
Levenberg-Marquardt algorithm
13-53
LEVIN model parameter
26-70
LEVOUT model parameter
26-70
.LIB
definition statement
3-33
with multiple .ALTER statements
3-42
.lib file encryption
E-11
libraries
building
with .LIB definition
3-33
duplicated parameter names
7-14
search
limit descriptors command
8-18
linear
region equations, MOSFETs LEVEL 47
22-14
technology device models
D-14
listing
LM capacitor parameter
15-6
local
lossless
parameter combinations
C-37
lossy
low-frequency large-signal characteristics
using Ebers-Moll model
16-5
LP capacitor parameter
15-6
LRD model parameter
20-29
LRS model parameter
20-29
Lsim models, calibrating
24-1
LV18 model parameter
31-7
M
multiplier parameter
macros
defining with .LIB definition
3-33
deleting library data
3-42
magnitude
MANU model parameter
26-70
manufacturing tolerances
13-21
Marquardt scaling parameter
13-53
mask (digital vector file)
5-73
matrix
MAX
optimization parameter
13-42
MAXD model parameter
C-15
MAXF
maximum
measure
data output formatting
9-7
MESFETs
CAPOP=2 model parameters
17-29
DC
model equation selector
17-13
models
n-channel specification
17-13
noise
p-channel specification
17-13
temperature
messages
Metaencrypt, character length restrictions
E-6
metal and poly capacitance equations
15-27
Meyer
and Charge Conservation Model parameters
8-64
capacitance
gate capacitances
microstrip transmission line
C-21
MIN
minimum
mixed
mixed mode
mixed-signal simulation
MJSW model parameter
20-28
mobility
equations, MOSFETs LEVEL 47
22-12
parameters
MOSFETs
reduction equations, MOSFETs
temperature equations, JFETs and MESFETs
17-44
.MODEL
model
inductors
model names, periods in
D-3
model parameters
base width modulation
16-9
high current Beta degradation
16-10
junction capacitance
16-11
low current Beta degradation
16-9
parasitics
temperature
capacitance distribution
13-24
diodes
Fowler-Nordheim diodes
15-48
geometry, JFETs and MESFETs
17-7
.GRAPH statement parameters
8-13
DC
See also
model parameters, JFETs or model parameters, MESFETs
manufacturing tolerances
13-21
metal and poly capacitors
15-13
sigma deviations, worst case analysis
13-9
suppressing printout of
9-8
temperature analysis
13-5
transmission lines
geometric
precomputed parameters
C-30
basic ELEV parameters
C-36
common planar parameters
C-24
geometric
model selection
failure to find a model
D-3
examples, NMOS model
22-53
ferromagnetic cores
14-12
HSPICE version parameter
3-31
optimization syntax
13-40
.MODEL statements and MESFETs
17-13
models
depletion MOS devices
20-3
device
equations
examples, Jiles-Atherton
14-20
ferromagnetic cores
14-19
ion-implanted devices
20-3
JFETs and MESFETs
Jiles-Atherton core
14-19
junction
Monte Carlo
parameter distribution
13-18
Berkeley
BSIM3v3
Frohman-Bentchkowski, equations
21-77
IDS
LEVEL 6
LEVEL 6 and LEVEL 7
21-52
LEVELs 49 and 53, equations
22-52
parameters
reference temperature
13-5
VBIC bipolar transistor
16-57
wire
modified BSIM LEVEL 28
MONO model parameter
8-13
Monte Carlo
MOS
op-amp optimization
13-70
MOSFETs
Berkeley
bulk transconductance
20-23
capacitance
effective length and width
20-97
channel length modulation temperature equations
20-111
charge
conservation model parameters
20-71
control options (list)
20-11
current
diodes
capacitance
DC
effective
GEO element parameter
20-42
geometry model parameters
20-30
model
resistance
drain diffusion area
4-19
effective
element
energy gap temperature equations
20-105
equation variables and constants
20-20
equivalent circuits
20-22
examples
gate
capacitance example
20-64
overlap capacitance model parameters
20-70
isoplanar
LEVELs 6, 7 UPDATE selector
21-57
Meyer capacitance model parameters
20-71
mobility temperature equations
20-111
model
model parameters
change conservation
20-71
effective width/length
21-9
gate capacitance
models
Berkeley
BSIM3v3
Dallas Semiconductor
20-5
Frohman-Bentchkowski, equations
21-77
IDS
LEVEL 6
Lattin-Jenkins-Grove
20-5
LEVELs 49 and 53 equations
22-52
National Semiconductor
20-6
quasi-static, equations
22-103
n-channel specification
20-14
p-channel specification
20-14
perimeter
saturation current temperature equations
20-106
source
drain sharing selector
4-20
squares
per source diffusion
4-19
surface potential temperature equations
20-109
temperature
coefficient model parameters
20-104
template input
threshold voltage
WIC ids current selector
21-73
zero-bias voltage threshold shift
4-20
MSPICE simulator interface
9-12
multiconductor capacitance/conductance
C-32
multiconductor systems
18-3
multiple .ALTER statements
3-42
multiplier
function, U and T Elements
C-5
G and E Element values
29-11
multipoint experiment
1-8
multi-terminal network
6-1
mutual
inductor
coupling coefficient
14-18
narrow width effect
21-13
natural
n-channel, MOSFET's models
3-30
NDS model parameter
20-27
negative conductance, logging
9-15
nested library calls
3-33
network
variable specification
12-18
nodes
connection requirements
3-17
cross-reference table
9-7
automatic generation
3-19
phase or magnitude difference
8-31
balancing input nodes
26-66
DC operating point initialization
10-10
noise
coupled line
equations
JFETs and MESFETs
equivalent circuits
20-25
models
MOSFETs
problems and solutions
25-3
NOISENPT
frequency Table Model
6-4
NonQuasi-Static (NQS) model
22-23
nonvolatile memory diodes
15-1
NORM FFT analysis keyword
28-7
norm of the gradient
13-53
Normal Field equations
21-78
NPWL
NMOS transistor function
26-10
NSUB model parameter
20-28
numbers
numerical
integration
obtaining customer support
vi
odelay (digital vector file)
5-73
OFF
one-dimensional function
5-25
.OP statement parameters
10-6
OPAMP element parameter
26-13
op-amps
automatic generation
26-5
common mode rejection ratio
26-68
compensation level selector
26-68
diode and BJT saturation current
26-69
excess phase parameter
26-69
input
bias offset current
26-70
level type selector
26-70
short circuit current
26-70
internal feedback compensation capacitance
26-68
JFETs saturation current
26-70
manufacturer's name
26-70
model
output
level type selector
26-70
power
subcircuit generator
26-5
temperature parameter
26-71
unity gain frequency
26-69
operating point
capacitance
.IC statement initialization
10-9
.NODESET statement initialization
10-10
numerical values of model internal variables
22-108
saturation / non-saturation flag
22-109
SPICE-like threshold voltage
22-108
transconductance efficiency factor
22-108
operating systems, HSPICE
1-6
operators
optimization
analysis statements
13-39
CMOS tristate buffer
13-55
convergence options
13-36
data-driven vs. s-parameters
13-61
MOS
magnitude and phase
13-61
measured vs. calculated
13-61
results
function evaluations
13-53
Marquadt scaling parameter
13-53
norm of the gradient
13-53
residual sum of squares
13-52
simulation accuracy
13-36
TDR
time
OPTIMIZE
ACCT, summary of job statistics
8-16
ALT999 or ALT9999, for output file name extension
8-14
CO, for printout width
8-14
INGOLD, for printout numerical format
8-15
keyword application table
9-3
POST, for high resolution graphics
8-15
options
.OPTIONS SEARCH statement
3-36
printing bisection results
30-8
oscillation
from simulation errors
C-61
oscillators
DELMAX option setting
11-26
out (digital vector file)
5-76
output
data
significant digits specification
9-8
version number, specifying
3-60
specifying variables
8-10
specifying significant digits for
9-8
outz (digital vector file)
5-76
overlay dielectric transmission line
C-21
overview
page eject, suppressing
9-8
PAR
parameters
capacitor
data
DC
frequency response table
29-9
high-current beta degradation
16-10
junction
setting
limit checking
low-current beta degradation
16-9
model
Jiles-Atherton core
14-16
overriding
Release 95.1 and earlier
7-19
temperature, JFETs and MESFETs
17-38
See also
model parameters, optimization parameters
parasitic
diode, MOSFETs LEVEL 39
21-198
resistance
temperature equations
PARMIN optimization parameter
13-43
passive device models
14-1
path numbers, printing
9-9
p-channel
simulation
peak-to-peak value, measuring
8-46
period (digital vector file)
5-71
peripheral component interconnect
permit.hsp file, encryption capability
E-7
PHA model parameter
20-28
phase
locked loop, BJT model
26-92
PHD model parameter
20-28
PHOTO model parameter
13-22
PHP model parameter
20-28
PHS model parameter
20-28
pin capacitance, plotting
24-6
pivot
PJ capacitor, parameter
15-6
planar conductor parameters
C-20
PLL
See
phase locked loop
plot
PMOS model
pn junction conductance
10-54
POLE
transconductance element statement
29-7
voltage gain element statement
29-7
poles and zeros, complex
29-30
pole/zero
example
active low-pass filter
27-15
CMOS differential amplifier
27-12
high-pass Butterworth filter
27-10
frequency
imaginary to real ratio
27-5
maximum
relative error tolerance
27-5
starting points, Muller algorithm
9-37
,
10-33
function, Laplace transform
29-7
transient responses
29-46
power
operating point table
10-6
PPWL
PMOS transistor function
26-10
PRD model parameter
20-29
print
printed circuit boards
printer, device specification
8-10
printout
PRS model parameter
20-29
recovery ramp duration
5-8
PWL
NMOS and PMOS transistor functions
26-10
sources, data driven
5-18
voltage controlled
PWR model parameter
26-70
quasi-saturation BJT model
16-50
quasi-static model equations
22-103
RAC model parameter
26-71
radix (digital vector file)
5-68
random limit parameter distribution
13-14
RC
network
analysis
RDC model parameter
20-29
real part of AC voltage
8-31
real vs. imaginary component ratio
9-36
,
10-32
RECT FFT analysis keyword
28-8
rectangle, defining
18-38
rectangular FFT window
28-4
reference
plane, transmission lines
C-5
regions charge equations, MOSFETs LEVEL 13
21-118
RELIN optimization parameter
13-43
RELOUT optimization parameter
13-43
residual sum of squares
13-52
resistance
MOSFETs model parameters
20-29
resistor
element template listings
8-55
model
node to bulk capacitance
4-3
wire model parameters
14-5
RLGC
RLOAD model parameter
5-54
rms value, measuring
8-46
roac model parameter
26-71
ROUT model parameter
26-71
RPI
Poli-Si model
RSC model parameter
20-29
Frequency Table Model
6-4
S parameter
S19NAME model parameter
5-55
S19VHI model parameter
5-55
S19VLO model parameter
5-55
S1NAME model parameter
5-54
S1VHI model parameter
5-55
S1VLO model parameter
5-55
saturable core
saturation
current temperature equations
temperature equations, BJTs
16-42
voltage (vdsat), BSIM LEVEL 13
21-115
voltage equations, MOSFETs
.SAVE statement parameter
10-13
scale
global SCALM override
20-12
MOSFETs capacitance parameters
20-68
JFETs and MESFETs scaling
17-6
parameter
in a diode model statement
15-4
overriding in a model
20-12
scattering (S) parameters
8-29
schematic
Schmitt trigger example
10-18
Schottky barrier diodes
15-1
search path, setting
3-37
sensitivity
factors, MOSFETs LEVEL 28
21-154
SFFM source function
SGS-Thomson MOS model
20-6
shape
short-channel effect
21-13
SHRINK
SIG
SIG1 model parameter
C-25
sigma model parameter, sweeping
24-4
sign
signal integrity
SIGNAME element parameter
5-54
signed power function
7-10
Signetics
silicon
controlled rectifier, behavioral
26-59
silicon-on-sapphire devices
20-3
Simpson Integration
20-86
simulation
circuits
with Signetics drivers
25-18
electrical measurements
31-20
ground bounce example
25-24
multiple analyses, .ALTER statement
3-40
performance, multithreading
3-63
results
reducing
3-22
,
9-41
,
9-42
,
9-44
,
9-45
,
9-47
,
9-48
,
11-11
,
11-12
,
11-17
,
11-19
,
11-20
,
11-22
,
11-36
,
29-48
single point experiment
1-8
single-frequency FM source function
5-20
sinusoidal source function
5-10
skew
skin effect
imaginary term handling
18-13
skin effect frequency
C-18
slope (digital vector file)
5-74
small-signal
SMOOTH element parameter
26-20
SONAME model parameter
5-54
source
SOVHI model parameter
5-54
SOVLO model parameter
5-54
SP12 model parameter
C-24
spatial extent of leading edge
C-83
SPICE
AC
MOSFETs
plot
UTRA model parameter
21-11
depletion capacitor model
17-5
Meyer gate capacitances
20-74
model parameters, MOSFETs LEVEL 39
21-182
SRN model parameter
26-71
SRNEG model parameter
26-71
SRP model parameter
26-71
SRPOS model parameter
26-71
Star-Hspice
Δ
L equation
21-85
START .FFT parameter
28-7
statements
call
statistics
capacitance equations
17-28
stimulus input files
26-4
stripline transmission line
C-21
subcircuits
changing in .ALTER blocks
3-41
creating reusable circuits
3-47
global versus local nodes
3-20
hierarchical parameters
3-48
power dissipation computation
8-25
.PRINT and .PLOT statements
3-49
printing path numbers
9-9
SUBS model parameter
16-2
substrate
capacitance equations
16-39
subthreshold current equations, MOSFETs
surface potential equations
20-109
sweep
switch-level MOSFET's example
5-39
Synopsys models, calibrating
24-1
lossless transmission line model
C-88
multiplier function M
C-5
transient effects modeling
C-75
target specification
8-40
TD
tdelay (digital vector file)
5-73
TDR
time domain reflectometry
25-9
TEM transmission lines
18-3
TEMP
temperature
BJTs
capacitance equations
16-46
energy gap equations
16-42
parasitic resistor equations
16-49
compensation
effect
parameters
equations
grading coefficient
15-32
JFETs
MOSFETs
channel length modulation
20-111
diode
optimizing coefficients
31-18
Temperature Variation Analysis
13-2
Texas Instruments device models
D-16
tfall (digital vector file)
5-75
THD (total harmonic distortion)
28-1
THK1 model parameter
C-24
THK2 model parameter
C-24
three-dimensional function
5-27
threshold
temperature equations, JFETs and MESFETs
17-44
voltage
parameters, MOSFETs
20-50
domain
TimeMill models, calibrating
24-1
TIMESCALE model parameter
5-55
timestep
minimum internal timestep
11-36
Minimum Timestep Coefficient
11-36
default control algorithm
11-29
local truncation error algorithm
11-34
TIMESTEP model parameter
5-55
timing
TMPDIR environment variable
1-12
topology
transconductance
inverse Laplace transform
29-33
transfer sign function
7-10
TRANSFORMER element parameter
26-14
transformer, behavioral
26-57
transient
MOSFETs, equivalent circuit
20-23
transistors
BJTs
isoplanar silicon gate
20-17
process parameters, MOSFETs
transit time
Transmission line
transmission line
resistive termination
6-8
transmission lines
capacitance
coax
common ground inductance
C-75
conductance definitions
C-32
conductor
coupled
delay too small warning
C-5
geometric parameters
C-17
HSPICE
integration
interconnect properties
C-3
loss
lossless
lossy
lumped
multiple
oscillation problems
C-60
planar
precomputed parameters
C-30
printed circuit boards
propagating a voltage step
18-6
reflection calculations
C-84
SIG conductivity parameter
C-89
skin effect frequency
C-18
timestep control errors
C-61
total conductor resistance
C-51
transient impedance effects
C-75
twinlead
W Element input properties
18-14
transverse electromagnetic (TEM) waves
18-3
TRAP algorithm
See
trapezoidal integration
trapezoidal integration
trigger specification
8-40
triode tube
trise (digital vector file)
5-75
tristate
triz (digital vector file)
5-76
truncation algorithm
11-33
tskip (digital vector file)
5-71
TSTEP
TTL
tunit (digital vector file)
5-70
tunnel diode behavioral
26-58
twinlead
two-dimensional function
5-26
lossy transmission line model
C-71
,
C-88
multiplier function M
C-5
transient effects modeling
C-75
transmission line
U models
conductor
dielectric
electrical specification format
C-13
external capacitance
C-15
number of
perturbation
reference plane
transmission line type selector
C-13
UIC
transient analysis parameter
11-3
uniform parameter distribution
13-14
unity gain frequency
31-20
Universal Field mobility reduction
21-79
University of California, Berkeley SOI model (BSIM3-SOI)
22-114
University of Florida SOI model
22-133
UNORM FFT analysis keyword
28-7
unprintable characters in input
3-3
MOSFETs LEVELs 6, 7
21-57
UTRA model parameter restriction
10-45
variables
changing in .ALTER blocks
3-41
variance, statistical
13-3
VBIC
model (vertical bipolar inter-company)
16-57
VCC model parameter
26-71
VCCS
See
voltage controlled current source
VCO
See
voltage controlled oscillator
VCR
See
voltage controlled resistor
VCVS
See
voltage controlled voltage source
VDBR model parameter
15-36
VDGR model parameter
15-36
VDSR model parameter
15-36
VEE model parameter
26-72
Verilog
version
VHDL models, calibrating
24-1
vih (digital vector file)
5-77
vil (digital vector file)
5-77
vname (digital vector file)
5-68
VNDS model parameter
20-27
Vnn node name in CSOS
3-19
voh (digital vector file)
5-79
vol (digital vector file)
5-79
voltage
controlled
element template listings
8-56
inverting comparator application
26-79
error tolerance
gain
JFETs and MESFETs DC models
17-31
minimum
MOSFETs model parameters
20-50
operating point table
10-7
tolerance
variable capacitance model
26-84
VON model parameter
26-72
VONEG model parameter
26-72
VOP model parameter
26-72
VOPOS model parameter
26-72
VOS model parameter
26-72
vref (digital vector file)
5-78
VREL model parameter
C-36
vth (digital vector file)
5-78
Vxxx source element statement
5-2
W capacitor parameter
15-6
W Element
RLGC
transmission line
RLGC
transmission line
all nodes connected together
10-47
floating power supply nodes
3-17
invalid value for CRATIO
14-3
IS parameter too small
15-10
limiting repetitions
9-15
misuse of VERSION parameter
3-31
resistance smaller than RESMIN
14-6
T-line delay too small
C-5
zero diagonal value detected
10-49
wave propagation, transmission lines
18-5
waveform
display
WDEL model parameter
20-30
WIC weak inversion current selector
21-73
.WIDTH statement
print control options
8-14
WINDOW .FFT parameter
28-8
model
capacitance
effective length and width
14-5
resistance calculation
14-5
WLUMP model parameter
C-15
WM capacitor parameter
15-6
WMLT model parameter
20-30
Worst Case Corners Analysis
13-2
WP capacitor parameter
15-6
WRD model parameter
20-29
WRS model parameter
20-29
XGRID model parameter
8-13
Xilinx device models
D-17
XMAX model parameter
8-13
XMIN model parameter
8-13
XPART CAPOP model parameter
20-72
XPHOTO model parameter
13-22
XQC CAPOP model parameter
20-72
XSCAL model parameter
8-13
Y parameter
YGRID model parameter
8-13
YMAX
YMIN
YSCAL model parameter
8-13
zero delay
Star-Hspice Manual - Release 2001.2 - June 2001