Solar resources / readings

To better the solar cells, to better the environment

Semiconductor technical resources:

• Special knowledge links ( Memory | SOI | Strained silicon | LOD )
• IRTS Road Map: http://public.itrs.net/Files/2001ITRS/Home.htm
• MIT OPEN COURSE (Free) http://www.twocw.net/ 
• Stanford EE Class Material: http://www-ee.stanford.edu/class_directory.php 
• Patent search: http://patft.uspto.gov/netahtml/search-bool.html
• IBM research resources: http://www.research.ibm.com/journal/rdimg.html
• 　
• Stanford Resources: http://www.km2000.us/articles/collectedtopics.htm 
• Solid State Circuit Soc. / IEEE: http://www.ewh.ieee.org/soc/sscs/chapter.htm
• IC knowledge: http://www.icknowledge.com/
• Bay Area Engineer 'GRID': http://www.ee.com/grid/grid04.01/sum.htm
• EE Times: http://www.eetimes.com/salarysurvey/2000/default.html
• IMEC: http://imec.be/wwwinter/mediacenter/en/SR2006/681414.html
• Dr. Shur's (RPI) Semiconductor Resources: http://nina.ecse.rpi.edu/shur/
• Nano Structure Conf.: jobresources/nsf_etc.htm
• US Research Resources: jobresources/nsf_etc.htm
• IEEE Explorer Resources: http://ieeexplore.ieee.org/Xref/DynWel.jsp
• Physics Resources: http://mastep.sjsu.edu/resources/physics.htm
• Finding area code in US: http://www.mmiworld.com/codelist.htm
• Patent / Interlecture Property: http://www.delphion.com/
• Face interview http://www.manchester.edu/OSD/Career/pages/Interviewing.html
• HSPICE manual  http://www.ece.cmu.edu/~ee762/hspice-docs/html/hspice_and_qrg/index.html  | 
• SPC http://www.sixsigmaspc.com/six-sigma/cpk-vs-ppm.html
•  

Readings and Knowledge on semiconductor and IC

• Trends in Integrated Circuits Technology
• MOS Gate Dielectric Technology: Part 1
• MOS Gate Dielectric Technology: Part 2
• Shallow Junctions/Ohmic Contacts
• Silicides & Metal gates
• Interconnect Scaling
• Aluminum Interconnect Technology
• Copper Interconnect Technology
• Low-K Dielectrics
• Ohmic Contacts
• Interconnect Scaling
• Power Modeling
• Interconnect Thermal Modeling
• Interconnect Scaling Thermal Issues
• How to use TSUPREM4 (Tutorial)
• Silicides
• AluminumInterconnect Technology
• Copper Interconnect Technology
• Device Isolation Technology
• Deposition and Planarization Technology
• Future Interconnect Technology
• Future Devices part 1
• Future Devices part 2
• Future Devices part 3
• Message from the Vice President, Science and Technology, IBM Research Division
• Preface
• Silicon CMOS devices beyond scaling
• Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations
• Germanium channel MOSFETs: Opportunities and challenges
• Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges
• Emerging nanoscale silicon devices taking advantage of nanostructure physics
• Optimizing CMOS technology for maximum performance
• High-performance CMOS variability in the 65-nm regime and beyond
• Product-representative “at speed” test structures for CMOS characterization
• Ultralow-voltage, minimum-energy CMOS
• Three-dimensional integrated circuits
• Scaling the gate dielectric:Materials,integration and reliability
• Introduction to Wafer Fab Processing: October 15-18, Austin, Texas
• IC Packaging Technology and Challenges Course: October 15-16, Austin, Texas
• IC Packaging Design and Modeling Course: October 17-19, Austin, Texas
• CMOS and BiCMOS Process Integration Course: October 22-24, Austin, Texas
• Failure and Yield Analysis Short Course: March 10-13, 2008, San Diego, California; May 26-29, 2008, Munich, Germany
• Semiconductor Reliability Short Course: March 24-26, 2008, San Diego, California; May 19-21, 2008, Munich, Germany