Hi all,

Here is a nice collection of Interview questions with reponses:

CMOS interview questions.

1) What is latch up?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS)

2) Why is NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.

Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile) , but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance) .

3) What is Noise Margin? Explain the procedure to determine Noise Margin

The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

example: NML is input start from low, where is the value cause the upset of the out put, in the vo-vin chart, start vin from lower side till the slope =1, NML=@slope1 - low (0v) = 2.3v; NMH the input start from high, where is the value to cause the upset of the output, start vin from vdd till slope is 1, NMH = high (vdd) - slope@1 = 1.7v

more:http://www.ece.unm.edu/~jimp/vlsi/slides/chap2_1.html 

4) Explain sizing of the inverter?

In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance.

5) How do you size NMOS and PMOS transistors to increase the threshold voltage?

6) What is Noise Margin? Explain the procedure to determine Noise Margin?

The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

7) What happens to delay if you increase load capacitance?

delay increases.

8) What happens to delay if we include a resistance at the output of a CMOS circuit?

Increases. (RC delay)

9) What are the limitations in increasing the power supply to reduce delay?

The delay can be reduced by increasing the power supply but if we do so the heating effect comes because of excessive power, to compensate this we have to increase the die size which is not practical.

10) How does Resistance of the metal lines vary with increasing thickness and increasing length?

R = ( *l) / A.

11) For CMOS logic, give the various techniques you know to minimize power consumption?

Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and the operating frequency.

12) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?

In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gates (approximately 10 times) .

13) Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

Because it can not drive the output load straight away, so we gradually increase the size to get an optimized performance.

14) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results.

15) Give the expression for CMOS switching power dissipation?

CV2

16) What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0) .Which results Vth2>Vth1.

17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

we try to reverse bias not the channel and the substrate but we try to maintain the drain,source junctions reverse biased with respect to the substrate so that we dont loose our current into the substrate.

18) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.

19) Which transistor has higher gain. BJT or MOS and why?

BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law.

20) Why do we gradually increase the size of inverters in buffer design when trying to drive a high capacitive load? Why not give the output of a circuit to one large inverter?

We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter? The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.So this results in slow raise or fall times .A unit inverter can drive approximately an inverter thats 4 times bigger in size. So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap. This is the prime reason behind going for progressive sizing.

21) In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos.What determines the size of pmos wrt nmos. Though this is a simple question try to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground ann PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node.

22) Why PMOS and NMOS are sized equally in a Transmission Gates?

In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility.

23) All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter?

I have seen similar Qs in some of the discussions. If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly degraded 0;

24) A good question on Layouts. Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?

a) In digital design, decide the height of standard cells you want to layout.It depends upon how big your transistors will be.Have reasonable width for VDD and GND metal paths.Maintaining uniform Height for all the cell is very important since this will help you use place route tool easily and also incase you want to do manual connection of all the blocks it saves on lot of area.

b) Use one metal in one direction only, This does not apply for metal 1. Say you are using metal 2 to do horizontal connections, then use metal 3 for vertical connections, metal4 for horizontal, metal 5 vertical etc...

c) Place as many substrate contact as possible in the empty spaces of the layout.

d) Do not use poly over long distances as it has huge resistances unless you have no other choice.

e) Use fingered transistors as and when you feel necessary.

f) Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

25) What is metastability? When/why it will occur?Different ways to avoid this?

Metastable state: A un-known state in between the two logical known states.This will happen if the O/P cap is not allowed to charge/discharge fully to the required logical levels.

One of the cases is: If there is a setup time violation, metastability will occur,To avoid this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states.

26) Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

The late coming signals are to be placed closer to the output node ie A should go to the nmos that is closer to the output.

Digital design interview questions & answers.

1) Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this?

Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.

Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state) ; at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

2) What is skew, what are problems associated with it and how to minimize it?

In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.

This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.

Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time

3) What is slack?

'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen'.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.

When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead) .

Slack = Tdead - Tact.

Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.

4) What is glitch? What causes it (explain with waveform) ? How to overcome it?

The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state

5) Given only two xor gates one must function as buffer and another as inverter?

Tie one of xor gates input to 1 it will act as inverter.

Tie one of xor gates input to 0 it will act as buffer.

6) What is difference between latch and flipflop?

The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

7) Build a 4:1 mux using only 2:1 mux?

Difference between heap and stack?

The Stack is more or less responsible for keeping track of what's executing in our code (or what's been "called") . The Heap is more or less responsible for keeping track of our objects (our data, well... most of it - we'll get to that later.) .

Think of the Stack as a series of boxes stacked one on top of the next. We keep track of what's going on in our application by stacking another box on top every time we call a method (called a Frame) . We can only use what's in the top box on the stack. When we're done with the top box (the method is done executing) we throw it away and proceed to use the stuff in the previous box on the top of the stack. The Heap is similar except that its purpose is to hold information (not keep track of execution most of the time) so anything in our Heap can be accessed at any time. With the Heap, there are no constraints as to what can be accessed like in the stack. The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet - we can grab what we need quickly. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it.

9) Difference between mealy and moore state machine?

A) Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer

B) Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges)

Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.

Adv and Disadv

In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level.

All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.

Moore machine: the outputs are properties of states themselves... which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output.The outputs are held until you go to some other state Mealy machine:

Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

10) Difference between onehot and binary encoding?

Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot.

A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.

A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in the design

FPGA vendors frequently recommend using a onehot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a onehot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, onehot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks

11) What are different ways to synchronize between two clock domains?

12) How to calculate maximum operating frequency?

13) How to find out longest path?

You can find answer to this in timing.ppt of presentations section on this site

14) Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up (the leading 0s cannot be used in more than one sequence) ?

15) How to achieve 180 deree exact phase shift?

Never tell using inverter

a) dcm's an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.

b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used.

16) What is significance of ras and cas in SDRAM?

SDRAM receives its address command in two address words.

It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS) .

Following the RAS command is the column address strobe (CAS) for latching the second address word.

Shortly after the RAS and CAS strobes, the stored data is valid for reading.

17) Tell some of applications of buffer?

a) They are used to introduce small delays

b) They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.

c) They are used to support high fanout,eg:bufg

18) Implement an AND gate using mux?

This is the basic question that many interviewers ask. for and gate, give one input as select line,incase if u r giving b as select line, connect one input to logic '0' and other input to a.

19) What will happen if contents of register are shifter left, right?

It is well known that in left shift all bits will be shifted left and LSB will be appended with 0 and in right shift all bits will be shifted right and MSB will be appended with 0 this is a straightforward answer

What is expected is in a left shift value gets Multiplied by 2 eg:consider 0000_1110=14 a left shift will make it 0001_110=28, it the same fashion right shift will Divide the value by 2.

20) Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?

RULES:

1) frequency(clk_A) = frequency(clk_B) / 4

2) period(en_B) = period(clk_A) * 100

3) duty_cycle(en_B) = 25%

Assume clk_B = 100MHz (10ns)

From (1) , clk_A = 25MHz (40ns)

From (2) , period(en_B) = 40ns * 400 = 4000ns, but we only output for

1000ns,due to (3) , so 3000ns of the enable we are doing no output work. Therefore, FIFO size = 3000ns/40ns = 75 entries

21) Design a four-input NAND gate using only two-input NAND gates.

A:Basically, you can tie the inputs of a NAND gate together to get an inverter, so...

22) Difference between Synchronous and Asynchronous reset.?

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.

The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.

Disadvantages of synchronous reset:

Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal.

Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock[ if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be removed prior to the resumption of the clock.

Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Asynchronous reset :

The biggest problem with asynchronous resets is the reset release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.

Disadvantages of asynchronous reset: ensure that the release of the reset can occur within one clock period. if the release of the reset occurred on or near a clock edge such that the flip-flops went metastable.

23) Why are most interrupts active low?

This answers why most signals are active low

If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. hence people prefer using active low signals.

24) Give two ways of converting a two input NAND gate to an inverter?

(a) short the 2 inputs of the nand gate and apply the single input to it.

(b) Connect the output to one of the input and the other to the input signal.

25) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

set up time: - the amount of time the data should be stable before the application of the clock signal, where as the hold time is the amount of time the data should be stable after the application of the clock. Setup time signifies maximum delay constraints; hold time is for minimum delay constraints. Setup time is critical for establishing the maximum clock frequency.

26) Differences between D-Latch and D flip-flop?

D-latch is level sensitive where as flip-flop is edge sensitive. Flip-flops are made up of latches.

27) What is a multiplexer?

Is combinational circuit that selects binary information from one of many input lines and directs it to a single output line. (2n =>n) .

28) How can you convert an SR Flip-flop to a JK Flip-flop?

By giving the feed back we can convert, i.e !Q=>S and Q=>R.Hence the S and R inputs will act as J and K respectively.

29) How can you convert the JK Flip-flop to a D Flip-flop?

By connecting the J input to the K through the inverter.

30) What is Race-around problem?How can you rectify it?

The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem.To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.

31) How do you detect if two 8-bit signals are same?

XOR each bits of A with B (for e.g. A[0] xor B[0] ) and so on.the o/p of 8 xor gates are then given as i/p to an 8-i/p nor gate. if o/p is 1 then A=B.

32) 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?

6 cycles

33) Convert D-FF into divide by 2. (not latch) What is the max clock frequency the circuit can handle, given the following information?

T_setup= 6nS T_hold = 2nS T_propagation = 10nS

Circuit: Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2. Max. Freq of operation: 1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

34) Guys this is the basic question asked most frequently. Design all the basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer?

Using 2:1 Mux, (2 inputs, 1 output and a select line)

(a) NOT

Give the input at the select line and connect I0 to 1 & I1 to 0. So if A is 1, we will get I1 that is 0 at the O/P.

(b) AND

Give input A at the select line and 0 to I0 and B to I1. O/p is A & B

(c) OR

Give input A at the select line and 1 to I1 and B to I0. O/p will be A | B

(d) NAND

AND + NOT implementations together

(e) NOR

OR + NOT implementations together

(f) XOR

A at the select line B at I0 and ~B at I1. ~B can be obtained from (a) (g) XNOR

A at the select line B at I1 and ~B at I0

35) N number of XNOR gates are connected in series such that the N inputs (A0,A1,A2......) are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate and so on..... Nth XNOR gates output is final output. How does this circuit work? Explain in detail?

If N=Odd, the circuit acts as even parity detector, ie the output will 1 if there are even number of 1's in the N input...This could also be called as odd parity generator since with this additional 1 as output the total number of 1's will be ODD.

If N=Even, just the opposite, it will be Odd parity detector or Even Parity Generator.

36) An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:

(i) If the emergency switch is pressed

(ii) If the senor1 and sensor2 are activated at the same time.

(iii) If sensor 2 and sensor3 are activated at the same time.

(iv) If all the sensors are activated at the same time

Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?

No of 2-input NAND Gates required = 6 You can try the whole implementation.

37) Design a circuit that calculates the square of a number? It should not use any multiplier circuits. It should use Multiplexers and other logic?

This is interesting....

1^2=0+1=1

2^2=1+3=4

3^2=4+5=9

4^2=9+7=16

5^2=16+9=25

and so on

See a pattern yet?To get the next square, all you have to do is add the next odd number to the previous square that you found.See how 1,3,5,7 and finally 9 are added.Wouldn't this be a possible solution to your question since it only will use a counter,multiplexer and a couple of adders?It seems it would take n clock cycles to calculate square of n.

38) How will you implement a Full subtractor from a Full adder?

all the bits of subtrahend should be connected to the xor gate. Other input to the xor being one.The input carry bit to the full adder should be made 1. Then the full adder works like a full subtractor

39) A very good interview question... What is difference between setup and hold time. The interviewer was looking for one specific reason , and its really a good answer too..The hint is hold time doesn't depend on clock, why is it so...?

Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup violation. But for hold time, you are only concerned with one edge and does not basically depend on clock frequency.

40) In a 3-bit Johnson's counter what are the unused states?

2(power n) -2n is the one used to find the unused states in johnson counter.

So for a 3-bit counter it is 8-6=2.Unused states=2. the two unused states are 010 and 101

41) The question is to design minimal hardware system, which encrypts 8-bit parallel data. A synchronized clock is provided to this system as well. The output encrypted data should be at the same rate as the input data but no necessarily with the same phase.

The encryption system is centered around a memory device that perform a LUT (Look-Up Table) conversion. This memory functionality can be achieved by using a PROM, EPROM, FLASH and etc. The device contains an encryption code, which may be burned into the device with an external programmer. In encryption operation, the data_in is an address pointer into a memory cell and the combinatorial logic generates the control signals. This creates a read access from the memory. Then the memory device goes to the appropriate address and outputs the associate data. This data represent the data_in after encryption. 41) What is an LFSR .List a few of its industry applications.?

LFSR is a linear feedback shift register where the input bit is driven by a linear function of the overall shift register value. coming to industrial applications, as far as I know, it is used for encryption and decryption and in BIST(built-in-self-test) based applications..

42) what is false path?how it determine in ckt? what the effect of false path in ckt?

By timing all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs.

An example of a false path is shown in figure below. The path going from the input A of the first MUX through the combinational logic out through the B input of the second MUS is a false path. This path can never be activated since if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX.

STA (Static Timing Analysis) tools are able to identify simple false paths; however they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable (sometimes faster)

43) Consider two similar processors, one with a clock skew of 100ps and other with a clock skew of 50ps. Which one is likely to have more power? Why?

Clock skew of 50ps is more likely to have clock power. This is because it is likely that low-skew processor has better designed clock tree with more powerful and number of buffers and overheads to make skew better.

44) What are multi-cycle paths?

Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.

For ex. Analyzing the design shown in fig below shows that the output SIN/COS requires 4 clock-cycles after the input ANGLE is latched in. This means that the combinatorial block (the Unrolled Cordic) can take up to 4 clock periods (25MHz) to propagate its result. Place and Route tools are capable of fixing multi-cycle paths problem.

45) You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is "ripple" (cascading) , Which circuit has a less propagation delay? Why?

The synchronous counter will have lesser delay as the input to each flop is readily available before the clock edge. Whereas the cascade counter will take long time as the output of one flop is used as clock to the other. So the delay will be propagating. For Eg: 16 state counter = 4 bit counter = 4 Flip flops Let 10ns be the delay of each flop The worst case delay of ripple counter = 10 * 4 = 40ns The delay of synchronous counter = 10ns only.(Delay of 1 flop)

46) what is difference between RAM and FIFO?

FIFO does not have address lines

Ram is used for storage purpose where as fifo is used for synchronization purpose i.e. when two peripherals are working in different clock domains then we will go for fifo.

47) The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotating.?

2 sensors are required to find out the direction of rotating. They are placed like at the drawing. One of them is connected to the data input of D flip-flop,and a second one - to the clock input. If the circle rotates the way clock sensor sees the light first while D input (second sensor) is zero - the output of the flip-flop equals zero, and if D input sensor "fires" first - the output of the flip-flop becomes high.

48) Draw timing diagrams for following circuit.?

49) Implement the following circuits:

(a) 3 input NAND gate using min no of 2 input NAND Gates

(b) 3 input NOR gate using min no of 2 inpur NOR Gates

(c) 3 input XNOR gate using min no of 2 inpur XNOR Gates

Assuming 3 inputs A,B,C?

3 input NAND:

Connect :

a) A and B to the first NAND gate

b) Output of first Nand gate is given to the two inputs of the second NAND gate (this basically realizes the inverter functionality)

c) Output of second NAND gate is given to the input of the third NAND gate, whose other input is C

((A NAND B) NAND (A NAND B) ) NAND C Thus, can be implemented using '3' 2-input NAND gates. I guess this is the minimum number of gates that need to be used.

3 input NOR:

Same as above just interchange NAND with NOR ((A NOR B) NOR (A NOR B) ) NOR C

3 input XNOR:

Same as above except the inputs for the second XNOR gate, Output of the first XNOR gate is one of the inputs and connect the second input to ground or logical '0'

((A XNOR B) XNOR 0) ) XNOR C

50) Is it possible to reduce clock skew to zero? Explain your answer ?

Even though there are clock layout strategies (H-tree) that can in theory reduce clock skew to zero by having the same path length from each flip-flop from the pll, process variations in R and C across the chip will cause clock skew as well as a pure H-Tree scheme is not practical (consumes too much area) .

51) Design a FSM (Finite State Machine) to detect a sequence 10110?

52) Convert D-FF into divide by 2. (not latch) ? What is the max clock frequency of the circuit , given the following information?

T_setup= 6nS

T_hold = 2nS

T_propagation = 10nS

Circuit:

Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2.

Max. Freq of operation:

1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

53) Give the circuit to extend the falling edge of the input by 2 clock pulses?The waveforms are shown in the following figure.

54) For the Circuit Shown below, What is the Maximum Frequency of Operation?Are there any hold time violations for FF2? If yes, how do you modify the circuit to avoid them?

The minumum time period = 3+2+(1+1+1) = 8ns Maximum Frequency = 1/8n= 125MHz.

And there is a hold time violation in the circuit,because of feedback, if you observe, tcq2+AND gate delay is less than thold2,To avoid this we need to use even number of inverters(buffers) . Here we need to use 2 inverters each with a delay of 1ns. then the hold time value exactly meets.

55) Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch ?

56) How to implement a Master Slave flip flop using a 2 to 1 mux?

57) how many 2 input xor's are needed to inplement 16 input parity generator ?

It is always n-1 Where n is number of inputs.So 16 input parity generator will require 15 two input xor's .

58) Design a circuit for finding the 9's compliment of a BCD number using 4-bit binary adder and some external logic gates?

9's compliment is nothing but subracting the given no from 9.So using a 4 bit binary adder we can just subract the given binary no from 1001(i.e. 9) .Here we can use the 2's compliment method addition.

59) what is Difference between writeback and write through cache?

A caching method in which modifications to data in the cache aren't copied to the cache source until absolutely necessary. Write-back caching is available on many microprocessors , including all Intel processors since the 80486. With these microprocessors, data modifications to data stored in the L1 cache aren't copied to main memory until absolutely necessary. In contrast, a write-through cache performs all write operations in parallel -- data is written to main memory and the L1 cache simultaneously. Write-back caching yields somewhat better performance than write-through caching because it reduces the number of write operations to main memory. With this performance improvement comes a slight risk that data may be lost if the system crashes.

A write-back cache is also called a copy-back cache.

60) Difference between Synchronous,Asynchronous & Isynchronous communication?

Sending data encoded into your signal requires that the sender and receiver are both using the same enconding/decoding method, and know where to look in the signal to find data. Asynchronous systems do not send separate information to indicate the encoding or clocking information. The receiver must decide the clocking of the signal on it's own. This means that the receiver must decide where to look in the signal stream to find ones and zeroes, and decide for itself where each individual bit stops and starts. This information is not in the data in the signal sent from transmitting unit.

Synchronous systems negotiate the connection at the data-link level before communication begins. Basic synchronous systems will synchronize two clocks before transmission, and reset their numeric counters for errors etc. More advanced systems may negotiate things like error correction and compression.

Time-dependent. it refers to processes where data must be delivered within certain time constraints. For example, Multimedia stream require an isochronous transport mechanism to ensure that data is delivered as fast as it is displayed and to ensure that the audio is synchronized with the video.

61) What are different ways Multiply & Divide?

Set quotient to zero

Repeat while dividend is greater than or equal to divisor

Subtract divisor from dividend

Add 1 to quotient

End of repeat block

quotient is correct, dividend is remainder

STOP

Binary Division by Shift and Subtract

Basically the reverse of the mutliply by shift and add.

Set quotient to 0

Align leftmost digits in dividend and divisor

Repeat

If that portion of the dividend above the divisor is greater than or equal to the divisor

Then subtract divisor from that portion of the dividend and

Concatentate 1 to the right hand end of the quotient

Else concatentate 0 to the right hand end of the quotient

Shift the divisor one place right

Until dividend is less than the divisor

quotient is correct, dividend is remainder

STOP

Binary Multiply - Repeated Shift and Add

Repeated shift and add - starting with a result of 0, shift the second multiplicand to correspond with each 1 in the first multiplicand and add to the result. Shifting each position left is equivalent to multiplying by 2, just as in decimal representation a shift left is equivalent to multiplying by 10.

Set result to 0

Repeat

Shift 2nd multiplicand left until rightmost digit is lined up with leftmost 1 in first multiplicand

Add 2nd multiplicand in that position to result

Remove that 1 from 1st multiplicand

Until 1st multiplicand is zero

Result is correct

STOP

62) What is a SoC (System On Chip) , ASIC, "full custom chip", and an FPGA?

There are no precise definitions. Here is my sense of it all. First, 15 years ago, people were unclear on exactly what VLSI meant. Was it 50000 gates? 100000 gates? was is just anything bigger than LSI? My professor simply told me that; VLSI is a level of complexity and integration in a chip that demands Electronic Design Automation tools in order to succeed. In other words, big enough that manually drawing lots of little blue, red and green lines is too much for a human to reasonably do. I think that, likewise, SoC is that level of integration onto a chip that demands more expertise beyond traditional skills of electronics. In other words, pulling off a SoC demands Hardware, Software, and Systems Engineering talent. So, trivially, SoCs aggressively combine HW/SW on a single chip. Maybe more pragmatically, SoC just means that ASIC and Software folks are learning a little bit more about each other's techniques and tools than they did before. Two other interpretations of SoC are 1) a chip that integrates various IP (Intellectual Property) blocks on it and is thus highly centered with issues like Reuse, and 2) a chip integrating multiple classes of electronic circuitry such as Digital CMOS, mixed-signal digital and analog (e.g. sensors, modulators, A/Ds) , DRAM memory, high voltage power, etc.

ASIC stands for "Application Specific Integrated Circuit". A chip designed for a specific application. Usually, I think people associate ASICs with the Standard Cell design methodology. Standard Cell design and the typical "ASIC flow" usually means that designers are using Hardware Description Languages, Synthesis and a library of primitive cells (e.g. libraries containing AND, NAND, OR, NOR, NOT, FLIP-FLOP, LATCH, ADDER, BUFFER, PAD cells that are wired together (real libraries are not this simple, but you get the idea..) . Design usually is NOT done at a transistor level. There is a high reliance on automated tools because the assumption is that the chip is being made for a SPECIFIC APPLICATION where time is of the essence. But, the chip is manufactured from scratch in that no pre-made circuitry is being programmed or reused. ASIC designer may, or may not, even be aware of the locations of various pieces of circuitry on the chip since the tools do much of the construction, placement and wiring of all the little pieces.

Full Custom, in contrast to ASIC (or Standard Cell) , means that every geometric feature going onto the chip being designed (think of those pretty chip pictures we have all seen) is controlled, more or less, by the human design. Automated tools are certainly used to wire up different parts of the circuit and maybe even manipulate (repeat, rotate, etc.) sections of the chip. But, the human designer is actively engaged with the physical features of the circuitry. Higher human crafting and less reliance on standard cells takes more time and implies higher NRE costs, but lowers RE costs for standard parts like memories, processors, uarts, etc.

FPGAs, or Field Programmable Gate Arrays are completely designed chips that designers load a programming pattern into to achieve a specific digital function. A bit pattern (almost like a software program) is loaded into the already manufactured device which essentially interconnects lots of available gates to meet the designers purposes. FPGAs are sometimes thought of as a "Sea of Gates" where the designer specifies how they are connected. FPGA designers often use many of the same tools that ASIC designers use, even though the FPGA is inherently more flexible. All these things can be intermixed in hybrid sorts of ways. For example, FPGAs are now available that have microprocessor embedded within them which were designed in a full custom manner, all of which now demands "SoC" types of HW/SW integration skills from the designer.

63) What is "Scan" ?

§Scan Insertion and ATPG helps test ASICs (e.g. chips) during manufacture. If you know what JTAG boundary scan is, then Scan is the same idea except that it is done inside the chip instead of on the entire board. Scan tests for defects in the chip's circuitry after it is manufactured (e.g. Scan does not help you test whether your Design functions as intended) . ASIC designers usually implement the scan themselves and occurs just after synthesis. ATPG (Automated Test Pattern Generation) refers to the creation of "Test Vectors" that the Scan circuitry enables to be introduced into the chip. Here's a brief summary:

· Scan Insertion is done by a tool and results in all (or most) of your design's flip-flops to be replaced by special "Scan Flip-flops". Scan flops have additional inputs/outputs that allow them to be configured into a "chain" (e.g. a big shift register) when the chip is put into a test mode.

· The Scan flip-flops are connected up into a chain (perhaps multiple chains)

· The ATPG tool, which knows about the scan chain you've created, generates a series of test vectors.

· The ATPG test vectors include both "Stimulus" and "Expected" bit patterns. These bit vectors are shifted into the chip on the scan chains, and the chips reaction to the stimulus is shifted back out again.

· The ATE (Automated Test Equipment) at the chip factory can put the chip into the scan test mode, and apply the test vectors. If any vectors do not match, then the chip is defective and it is thrown away.

· Scan/ATPG tools will strive to maximize the "coverage" of the ATPG vectors. In other words, given some measure of the total number of nodes in the chip that could be faulty (shorted, grounded, "stuck at 1", "stuck at 0") , what percentage of them can be detected with the ATPG vectors? Scan is a good technology and can achive high coverage in the 90% range.

· Scan testing does not solve all test problems. Scan testing typically does not test memories (no flip-flops!) , needs a gate-level netlist to work with, and can take a long time to run on the ATE.

· FPGA designers may be unfamiliar with scan since FPGA testing has already been done by the FPGA manufacturer. ASIC designers do not have this luxury and must handle all the manufacturing test details themselves.

· Check out the Synopsys WWW site for more info.

1) Write a verilog code to swap contents of two registers with and without a temporary register?

With temp reg ;

always @ (posedge clock)

begin

temp=b;

b=a;

a=temp;

end

Without temp reg;

always @ (posedge clock)

begin

a <= b; b <= a; end 2) Difference between blocking and non-blocking?(Verilog interview questions that is most commonly asked)

The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program // testing blocking and non-blocking assignment module blocking; reg [0] A, B; initial begin: init1 A = 3; #1 A = A + 1; // blocking procedural assignment B = A + 1; $display("Blocking: A= %b B= %b", A, B ) ; A = 3; #1 A <= A + 1; // non-blocking procedural assignment

B <= A + 1; #1 $display("Non-blocking: A= %b B= %b", A, B ) ; end endmodule produces the following output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100 The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems. blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential

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Difference between task and function?

Function:

A function is unable to enable a task however functions can enable other functions.

A function will carry out its required duty in zero simulation time. ( The program time will not be incremented during the function routine)

Within a function, no event, delay or timing control statements are permitted

In the invocation of a function their must be at least one argument to be passed.

Functions will only return a single value and can not use either output or inout statements.

Tasks:

Tasks are capable of enabling a function as well as enabling other versions of a Task

Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time.

Tasks are allowed to contain any of these statements.

A task is allowed to use zero or more arguments which are of type output, input or inout.

A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements .

4) Difference between inter statement and intra statement delay?

//define register variables

reg a, b, c;

//intra assignment delays

initial

begin

a = 0; c = 0;

b = #5 a + c; //Take value of a and c at the time=0, evaluate

//a + c and then wait 5 time units to assign value

//to b.

end

//Equivalent method with temporary variables and regular delay control

initial

begin

a = 0; c = 0;

temp_ac = a + c;

#5 b = temp_ac; //Take value of a + c at the current time and

//store it in a temporary variable. Even though a and c

//might change between 0 and 5,

//the value assigned to b at time 5 is unaffected.

end

5) What is delta simulation time?

6) Difference between $monitor,$display & $strobe?

These commands have the same syntax, and display text on the screen during simulation. They are much less convenient than waveform display tools like cwaves?. $display and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters changes.

The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than exactly where it is executed. The format string is like that in C/C++, and may contain format characters. Format characters include %d (decimal) , %h (hexadecimal) , %b (binary) , %c (character) , %s (string) and %t (time) , %m (hierarchy level) . %5d, %5b etc. would give exactly 5 spaces for the number instead of the space needed. Append b, h, o to the task name to change default format to binary, octal or hexadecimal.

Syntax:

$display ("format_string", par_1, par_2, ... ) ;

$strobe ("format_string", par_1, par_2, ... ) ;

$monitor ("format_string", par_1, par_2, ... ) ;

7) What is difference between Verilog full case and parallel case?

A "full" case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If a case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not "full."

A "parallel" case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case expression that would match more than one case item, the matching case items are called "overlapping" case items and the case statement is not "parallel."

8) What is meant by inferring latches,how to avoid it?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0})

2'd0 : out = i0;

2'd1 : out = i1;

2'd2 : out = i2;

endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified.

For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.

The same may be observed in IF statement in case an ELSE IF is not specified.

To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

9) Tell me how blocking and non blocking statements get executed?

Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of nonblocking statements at the end of the time step.

10) Variable and signal which will be Updated first?

Signals

11) What is sensitivity list?

The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed.

12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

13) Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation

`timescale 1 ns / 10 ps

module name (input and outputs) ;

// parameter declarations

parameter parameter_name = parameter value;

// Input output declarations

input in1;

input in2; // single bit inputs

output [msb] out; // a bus output

// internal signal register type declaration - register types (only assigned within always statements) . reg register variable 1;

reg [msb] register variable 2;

// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;

// hierarchy - instantiating another module

reference name instance name (

.pin1 (net1) ,

.pin2 (net2) ,

.

.pinn (netn)

) ;

// synchronous procedures

always @ (posedge clock)

begin

.

end

// combinatinal procedures

always @ (signal1 or signal2 or signal3)

begin

.

end

assign net variable = combinational logic;

endmodule

14) Difference between Verilog and vhdl?

Compilation

VHDL. Multiple design-units (entity/architecture pairs) , that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

15) What are different styles of Verilog coding I mean gate-level,continuous level and others explain in detail?

16) Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $display.This can be used for displaying strings, expression or values of variables.

Here are some examples of usage.

$display("Hello oni") ;

--- output: Hello oni

$display($time) // current simulation time.

--- output: 460

counter = 4'b10;

$display(" The count is %b", counter) ;

--- output: The count is 0010

$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the

user can enter commands; $finish exits the simulator back to the operating system

17) Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,

Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below

module memory (

input r,

input wr,

input [7] data_in,

input [3] addr,

output [7] data_out

) ;

18) Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:

always @ (posedge clk )

begin if (reset)

. . . end

Asynchronous means clock independent so reset must be present in sensitivity list.

Eg

Always @(posedge clock or posedge reset)

begin

if (reset)

. . . end

19) What is pli?why is it used?

Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program.

PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related features of Verilog and sequential flow of C - using PLI.

20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide?

Ants can move only along edges of triangle in either of direction, let's say one is represented by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants are going in same direction they won't collide that is 111 or 000 so probability of collision is 2/8=1/4

21) Tell me about file I/O?

21) What is difference between freeze deposit and force?

$deposit(variable, value) ;

This system task sets a Verilog register or net to the specified value. variable is the

register or net to be changed; value is the new value for the register or net. The value

remains until there is a subsequent driver transaction or another $deposit task for the

same register or net. This system task operates identically to the ModelSim

force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is

specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved

signals. This is designed to provide compatibility with force files. But if you prefer -freeze

as the default for both resolved and unresolved signals.

Verilog interview Questions

22) Will case infer priority register if yes how give an example?

yes case can infer priority register depending on coding style

reg r;

// Priority encoded mux,

always @ (a or b or c or select2)

begin

r = c;

case (select2)

2'b00: r = a;

2'b01: r = b;

endcase

end

Verilog interview Questions

23) Casex,z difference,which is preferable,why?

CASEZ :

Special version of the case statement which uses a Z logic value to represent don't-care bits. CASEX :

Special version of the case statement which uses Z or X logic values to represent don't-care bits.

CASEZ should be used for case statements with wildcard don't cares, otherwise use of CASE is required; CASEX should never be used.

This is because:

Don't cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will automatically match any x or z with anything in the case statement. Casez will only match z's -- x's require an absolute match.

Verilog interview Questions

24) Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;

a <= 1; $display(a) ; end This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time: 1: Active Events (blocking statements) 2: Inactive Events (#0 delays, etc) 3: Non-Blocking Assign Updates (non-blocking statements) 4: Monitor Events ($display, $monitor, etc) . Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1. 25) What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;".

a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.

26) What is the difference between:

c = foo ? a : b;

and

if (foo) c = a;

else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

27) What are Intertial and Transport Delays ??

28) What does `timescale 1 ns/ 1 ps signify in a verilog code?

'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage : `timescale

34) what is verilog case (1) ?

wire [3] x;

always @(...) begin

case (1'b1)

x[0]: SOMETHING1;

x[1]: SOMETHING2;

x[2]: SOMETHING3;

x[3]: SOMETHING4;

endcase

end

The case statement walks down the list of cases and executes the first one that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or selected by the logic) .

35) Why is it that "if (2'b01 & 2'b10) ..." doesn't run the true case?

This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&) .

36) What are Different types of Verilog Simulators ?

There are mainly two types of simulators available.

Event Driven

Cycle Based

Event-based Simulator:

This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagate .........

SOURCE:

http://vlsiques.blogspot.com/

I hope you liked

y ) process variation

z ) stage ratio

http://nanovlsi.blogspot.com/

• MTBF-Mean Time Before Failure

• Average time to next failure

• Lowering clock frequency
• Lowering data speed
• Using faster flip flop

• No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care).

• Simulation of synchronous reset is easy.

• Synchronous reset is slow.

• Implementation of synchronous reset requires more number of gates compared to asynchronous reset design.

• An active clock is essential for a synchronous reset design. Hence you can expect more power consumption.

• Implementation of asynchronous reset requires less number of gates compared to synchronous reset design.

• Asynchronous reset is fast.

• Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.

• Metastability problems are main concerns of asynchronous reset scheme (design).

• Static timing analysis and DFT becomes difficult due to asynchronous reset.

• Process
• Voltage
• Temperature

• Verilog and VHDL both are concurrent languages.

• Any hardware descriptive language is concurrent in nature.

• No.

• Making data path slower can help hold time but it may result in setup violation.

• Yes.

• Making data path faster can also help setup time but it may result in hold violation.

Physical Design Objective Type of Questions and Answers

• 1) Chip utilization depends on ___.

• 2) In Soft blockages ____ cells are placed.

• 3) Why we have to remove scan chains before placement?

• 4) Delay between shortest path and longest path in the clock is called ____.

• 5) Cross talk can be avoided by ___.

• 6) Prerouting means routing of _____.

• 7) Which of the following metal layer has Maximum resistance?

• 8) What is the goal of CTS?

• 9) Usually Hold is fixed ___.

• 10) To achieve better timing ____ cells are placed in the critical path.

• 11) Leakage power is inversely proportional to ___.

• 12) Filler cells are added ___.

• 13) Search and Repair is used for ___.

• 14) Maximum current density of a metal is available in ___.

• 15) More IR drop is due to ___.

• 16) The minimum height and width a cell can occupy in the design is called as ___.

• 17) CRPR stands for ___.

• 18) In OCV timing check, for setup time, ___.

• 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

• 20) The Solution for Antenna effect is ___.

• 21) To avoid cross talk, the shielded net is usually connected to ___.

• 22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

• 23) Hold violations are preferred to fix ___.

• 24) Which of the following is not present in SDC ___?

• 25) Timing sanity check means (with respect to PD)___.

• 26) Which of the following is having highest priority at final stage (post routed) of the design ___?

• 27) Which of the following is best suited for CTS?

• 28) Max voltage drop will be there at(with out macros) ___.

• 29) Which of the following is preferred while placing macros ___?

• 30) Routing congestion can be avoided by ___.

• 31) Pitch of the wire is ___.

• 32) In Physical Design following step is not there ___.

• 33) In technology file if 7 metals are there then which metals you will use for power?

• 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

• 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

• 36) Difference between Clock buff/inverters and normal buff/inverters is __.

• 37) Which configuration is more preferred during floorplaning ?

• 38) What is the effect of high drive strength buffer when added in long net?

• 39) Delay of a cell depends on which factors ?

• 40) After the final routing the violations in the design ___.

• 41) Utilisation of the chip after placement optimisation will be ___.

• 42) What is routing congestion in the design?

• 43) What are preroutes in your design?

• 44) Clock tree doesn't contain following cell ___.

• Answers:

CMOS Design Interview Questions

In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves?

What you mean by scan chain reordering?

Intel interview questions

VLSI Design Interview questions

Verilog Interview Questions

• What is the difference between $display and $monitor and $write and $strobe?
• What is the difference between code-compiled simulator and normal simulator?
• What is the difference between wire and reg?
• What is the difference between blocking and non-blocking assignments?
• What is the significance Timescale directivbe?
• What is the difference between bit wise, unary and logical operators?
• What is the difference between task and function?
• What is the difference between casex, casez and case statements?
• Which one preferred-casex or casez?
• For what is defparam used?
• What is the difference between “= =” and “= = =” ?
• What is a compiler directive like ‘include’ and ‘ifdef’?
• Write a verilog code to swap contents of two registers with and without a temporary register?
• What is the difference between inter statement and intra statement delay?
• What is delta simulation time?
• What is difference between Verilog full case and parallel case?
• What you mean by inferring latches?
• How to avoid latches in your design?
• Why latches are not preferred in synthesized design?
• How blocking and non blocking statements get executed?
• Which will be updated first: is it variable or signal?
• What is sensitivity list?
• If you miss sensitivity list what happens?
• In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
• What is general structure of Verilog code you follow?
• What are the difference between Verilog and VHDL?
• What are system tasks?
• List some of system tasks and what are their purposes?
• What are the enhancements in Verilog 2001?
• Write a Verilog code for synchronous and asynchronous reset?
• What is pli? why is it used?
• What is file I/O?
• What is difference between freeze deposit and force?
• Will case always infer priority register? If yes how? Give an example.
• What are inertial and transport delays ?
• What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
• How to generate sine wav using verilog coding style?
• How do you implement the bi-directional ports in Verilog HDL?
• How to write FSM is verilog?
• What is verilog case (1)?
• What are Different types of Verilog simulators available?
• What is Constrained-Random Verification ?
• How can you model a SRAM at RTL Level?

Physical Design Questions and Answers

• I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy !

• Chip design has I/O pads; block design has pins.

• Chip design uses all metal layes available; block design may not use all metal layers.

• Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.

• Chip design requires several packaging; block design ends in a macro.

• First check flylines i.e. check net connections from macro to macro and macro to standard cells.

• If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.

• If input pin is connected to macro better to place nearer to that pin or pad.

• If macro has more connection to standard cells spread the macros inside core.

• Avoid criscross placement of macros.

• Use soft or hard blockages to guide placement engine.

• Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.

• Hierarchical design takes more run time; Flattened design takes less run time.

• 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

• Herculis from Synopsys, Caliber from Mentor Graphics.

• Netlist, Technology library, Constraints, SPEF or SDF file.

• Provide soft or hard blockage

• By checking the total area of the design you can decide die size.

• Poly

• Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

• Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!

• Metal layers: See your tech file. generally for 90nm it is 7 to 9.

• Technology: Again look into tech files.

• Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc

• Clocks: Look into your design and SDC file !

• You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

• Depends on your design.

• For synthesis: RTL, Technology library, Standard cell library, Constraints

• For Physical design: Netlist, Technology library, Constraints, Standard cell library

• Clock definitions

• Timing exception-multicycle path, false path

• Input and Output delays

• Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.

• Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

• Prelayout: Setup, Max transition, max capacitance

• Post layout: Hold

• Setup: upsize the cells

• Hold: insert buffers

• Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

• Output pin.

• Increase power metal layer width.

• Go for higher metal layer.

• Spread macros or standard cells.

• Provide more straps.

• Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.

• Decrease the length of the net by providing more vias and layer jumping.

• Insert antenna diode.

• P increase->dealy increase

• P decrease->delay decrease

• V increase->delay decrease

• V decrease->delay increase

• T increase->delay increase

• T decrease->delay decrease

Physical Design Flow

The physical design flow is generally explained in the Figure (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirements
　

• Gate delay

• Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

• Gate delay =function of(i/p transition time, Cnet+Cpin).

• Cell delay is also same as Gate delay.

• Cell delay

• For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

• Intrinsic delay

• Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

• It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

• This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

• Net Delay (or wire delay)

• The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

• It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

• Wire delay =fn(Rnet , Cnet+Cpin)

• Linear Delay Model (LDM)

• Non Linear Delay Model (NLDM)

• Wire load model is NLDM which has estimated R and C of the net.

• Because it has less resistance and hence leads to less IR drop.

• Upsizing

• Downsizing

• Buffer insertion

• Buffer relocation

• Dummy buffer placement

• negative slack==> there is setup voilation==> deisgn can fail

• IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.

• If Idrop is more==>delay increases.

• crosstalk==>there can be setup as well as hold voilation.

• There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.

• If IR drop is more==>delay increases.

• Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.

• Affects: Either short or open of the signal line or power line.

• Global Routing

• Track Assignment

• Detail Routing

• Source Latency

• It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

• Delay from clock source to beginning of clock tree (i.e. clock definition point).

• The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

• Network latency

• It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

• The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

• Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

• If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

• Routing

• Distribution of clock from the clock source to the sync pin of the registers.

• H tree, Balanced tree, X tree, Clustering tree, Fish bone

• Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.

• Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

• Source Delay/Latency

• Network Delay/Latency

• Insertion Delay

• Transition Delay/Slew: Rise time, fall time

• Path Delay

• Net delay, wire delay, interconnect delay

• Propagation Delay

• Phase Delay

• Cell Delay

• Intrinsic Delay

• Extrinsic Delay

• Input Delay

• Output Delay

• Exit Delay

• Latency (Pre/post CTS)

• Uncertainty (Pre/Post CTS)

• Unateness: Positive unateness, negative unateness

• Jitter: PLL jitter, clock jitter

• Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

• Gate delay =function of(i/p transition time, Cnet+Cpin).

• Cell delay is also same as Gate delay.

• It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

• Delay from clock source to beginning of clock tree (i.e. clock definition point).

• The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

• It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

• The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

• The delay from the clock definition point to the clock pin of the register.

• It is also known as "Slew". It is defined as the time taken to change the state of the signal. Time taken for the transition from logic 0 to logic 1 and vice versa . or Time taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa.

• Transition is the time it takes for the pin to change state.

• Rate of change of logic.See Transition delay.

• Slew rate is the speed of transition measured in volt / ns.

• Rise time is the difference between the time when the signal crosses a low threshold to the time when the signal crosses the high threshold. It can be absolute or percent.

• Low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.

• Fall time is the difference between the time when the signal crosses a high threshold to the time when the signal crosses the low threshold.

• The low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.

• For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric triangular wave, this is reduced to just 50%.

• The rise/fall definition is set on the meter to 10% and 90% based on the linear power in Watts. These points translate into the -10 dB and -0.5 dB points in log mode (10 log 0.1) and (10 log 0.9). The rise/fall time values of 10% and 90% are calculated based on an algorithm, which looks at the mean power above and below the 50% points of the rise/fall times
• Path delay

• Path delay is also known as pin to pin delay. It is the delay from the input pin of the cell to the output pin of the cell.

• The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

• It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

• Wire delay =fn(Rnet , Cnet+Cpin)

• For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

• This is the time required for a signal to propagate through a gate or net. For gates it is the time it takes for a event at the gate input to affect the gate output.

• For net it is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

• It is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

• Same as insertion delay

• For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

• Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

• It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

• This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

• Same as wire delay, net delay, interconnect delay, flight time.

• Extrinsic delay is the delay effect that associated to with interconnect. output pin of the cell to the input pin of the next cell.

• Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock.

• Output delay is time required by the external circuit before which the data has to arrive at the output pin of the block with respect to reference clock.

• It is defined as the delay in the longest path (critical path) between clock pad input and an output. It determines the maximum operating frequency of the design.

• Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered.

• Uncertainty is the amount of skew and the variation in the arrival clock edge. Pre CTS uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew + Jitter.

• A function is said to be unate if the rise transition on the positive unate input variable causes the ouput to rise or no change and vice versa.

• Negative unateness means cell output logic is inverted version of input logic. eg. In inverter having input A and output Y, Y is -ve unate w.r.to A. Positive unate means cell output logic is same as that of input.

• These +ve ad -ve unateness are constraints defined in library file and are defined for output pin w.r.to some input pin.

• A clock signal is positive unate if a rising edge at the clock source can only cause a rising edge at the register clock pin, and a falling edge at the clock source can only cause a falling edge at the register clock pin.

• A clock signal is negative unate? if a rising edge at the clock source can only cause a falling edge at the register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock pin. In other words, the clock signal is inverted.

• A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the clock path. For example, a clock that passes through an XOR gate is not unate because there are nonunate arcs in the gate. The clock sense could be either positive or negative, depending on the state of the other input to the XOR gate.

• The short-term variations of a signal with respect to its ideal position in time.

• Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value.

• From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform.

• Internal circuitry of the phase-locked loop (PLL)

• Random thermal noise from a crystal

• Other resonating devices

• Random mechanical noise from crystal vibration

• Signal transmitters

• Traces and cables

• Connectors

• Receivers

• The difference in the arrival of clock signal at the clock pin of different flops.

• Two types of skews are defined: Local skew and Global skew.

• The difference in the arrival of clock signal at the clock pin of related flops.

• The difference in the arrival of clock signal at the clock pin of non related flops.

• Skew can be positive or negative.

• When data and clock are routed in same direction then it is Positive skew.

• When data and clock are routed in opposite then it is negative skew.

• Recovery specifies the minimum time that an asynchronous control input pin must be held stable after being de-asserted and before the next clock (active-edge) transition.

• Recovery time specifies the time the inactive edge of the asynchronous signal has to arrive before the closing edge of the clock.

• Recovery time is the minimum length of time an asynchronous control signal (eg.preset) must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals.

• Recovery Slack Time = Data Required Time – Data Arrival Time

• Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq+ Register to Register Delay

• Data Required Time = Latch Edge + Clock Network Delay to Destination Register =Tsetup

• Recovery Slack Time = Data Required Time – Data Arrival Time

• Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay

• Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay+Tsetup

• If the asynchronous reset signal is from a port (device I/O), you must make an Input Maximum Delay assignment to the asynchronous reset pin to perform recovery analysis on that path.

• Removal specifies the minimum time that an asynchronous control input pin must be held stable before being de-asserted and after the previous clock (active-edge) transition.

• Removal time specifies the length of time the active phase of the asynchronous signal has to be held after the closing edge of clock.

• Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. Calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous control is registered, equations shown in Equation 3 is used to calculate the removal slack time.

• If the recovery or removal minimum time requirement is violated, the output of the sequential cell becomes uncertain. The uncertainty can be caused by the value set by the resetbar signal or the value clocked into the sequential cell from the data input.

• Removal Slack Time = Data Arrival Time – Data Required Time

• Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq of Source Register + Register to Register Delay

• Data Required Time = Latch Edge + Clock Network Delay to Destination Register + Thold

• If the asynchronous control is not registered, equations shown in Equation 4 is used to calculate the removal slack time.

• Removal Slack Time = Data Arrival Time – Data Required Time

• Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay

• Data Required Time = Latch Edge + Clock Network Delay to Destination Register +Thold

• If the asynchronous reset signal is from a device pin, you must specify the Input Minimum Delay constraint to the asynchronous reset pin to perform a removal analysis on this path.

What is the difference between soft macro and hard macro?

• What is the difference between hard macro, firm macro and soft macro?

• What are IPs?

• Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other designs.

• Soft macros are in synthesizable RTL.

• Soft macros are more flexible than firm or hard macros.

• Soft macros are not specific to any manufacturing process.

• Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power.

• Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data.

• From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro Rail user manual !)

• Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

• Firm macros are in netlist format.

• Firm macros are optimized for performance/area/power using a specific fabrication technology.

• Firm macros are more flexible and portable than hard macros.

• Firm macros are predictive of performance and area than soft macros.

• Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !).

• Hard macos are targeted for specific IC manufacturing technology.

• Hard macros are block level designs which are silicon tested and proved.

• Hard macros have been optimized for power or area or timing.

• In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way.

• You have freedom to move, rotate, flip but you can't touch anything inside hard macros.

• Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general).. for example it can be a MP4 decoder.

• Be aware of features and characteristics of hard macro before you use it in your design... other than power, timing and area you also should know pin properties like sync pin, I/O standards etc

• LEF, GDS2 file format allows easy usage of macros in different tools.

• Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in Magma) as a GDS2 file.

What is the difference between FPGA and CPLD?

• FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once.

• The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

• Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA.

• FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this.

• FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500>

• Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment).

• Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue.

• Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families.

• Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage.

• Use FPGAs for larger and more complex designs.

• FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result.

What is the difference between FPGA and ASIC?

• Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.

• Field Programable Gate Arrays

• Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!

• No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!

• Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

• More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

• Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

• Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

• Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

• FPGA sythesis is much more easier than ASIC.

• In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

• Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

• You have to use the resources available in the FPGA. Thus FPGA limits the design size.

• Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

• Application Specific Intergrated Circiut

• Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

• Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

• Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

• In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

• In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

• Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

• Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)

• Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

• Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.

• Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.

• Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.

ASIC Design Check List

• What exact process are you using?
• How many layers can be used for this design?
• Are the Cross talk Noise constraints, Xtalk Analysis configuration, Cell EM & Wire EM available?

• What is the design application?
• Number of cells (placeable objects)?
• Is the design Verilog or VHDL?
• Is the netlist flat or hierarchical?
• Is there RTL available?
• Is there any datapath logic using special datapath tools?
• Is the DFT to be considered?
• Can scan chains be reordered?
• Is memory BIST, boundary scan used on this design?
• Are static timing analysis constraints available in SDC format?

• How many clock domains are in the design?
• What are the clock frequencies?
• Is there a target clock skew, latency or other clock requirements?
• Does the design have a PLL?
• If so, is it used to remove clock latency?
• Is there any I/O cell in the feedback path?
• Is the PLL used for frequency multipliers?
• Are there derived clocks or complex clock generation circuitry?
• Are there any gated clocks?
• If yes, do they use simple gating elements?
• Is the gate clock used for timing or power?
• For gated clocks, can the gating elements be sized for timing?
• Are you muxing in a test clock or using a JTAG clock?
• Available cells for clock tree?
• Are there any special clock repeaters in the library?
• Are there any EM, slew or capacitance limits on these repeaters?
• How many drive strengths are available in the standard buffers and inverters?
• Do any of the buffers have balanced rise and fall delays?
• Any there special requirements for clock distribution?
• Will the clock tree be shielded? If so, what are the shielding requirements?

• Target die area?
• Does the area estimate include power/signal routing?
• What gates/mm2 has been assumed?
• Number of routing layers?
• Any special power routing requirements?
• Number of digital I/O pins/pads?
• Number of analog signal pins/pads?
• Number of power/ground pins/pads?
• Total number of pins/pads and Location?
• Will this chip use a wire bond package?
• Will this chip use a flip-chip package?
• If Yes, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide?
• Have you already done floorplanning for this design?
• If yes, is conformance to the existing floorplan required?
• What is the target die size?
• What is the expected utilization?
• Please draw the overall floorplan ?
• Is there an existing floorplan available in DEF?
• What are the number and type of macros (memory, PLL, etc.)?
• Are there any analog blocks in the design?
• What kind of packaging is used? Flipchip?
• Are the I/Os periphery I/O or area I/O?
• How many I/Os?
• Is the design pad limited?
• Power planning and Power analysis for this design?
• Are layout databases available for hard macros ?
• Timing analysis and correlatio?
• Physical verification ?

• Library information for new library
• .lib for timing information
• GDSII or LEF for library cells including any RAMs
• RTL in Verilog/VHDL format
• Number of logical blocks in the RTL
• Constraints for the block in SDC
• Floorplan information in DEF
• I/O pin location
• Macro locations

ASIC General

• What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?
• In system with insufficient hold time, will slowing down the clock help?
• In system with insufficient setup time, will slowing down the clock help?
• Why would a testbench not have pins (port) on it?
• When declaring a flip flop, why would not you declare its output value in the port statement?
• Give 2 advantages of using a script to build a chip?
• A “tri state “ bus is directly connected to a set of CMOS input buffers. No other wires or components are attached to the bus wires. Upon observation we can find that under certain conditions, this circuit is consuming considerable power. Why it is so? Is circuit correct? If not, how to correct?
• Is Verilog (or that matter any HDL) is a concurrent or sequential language?
• What is the function of sensitivity list?
• A mealy –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?
• A moore –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly?
• What type of delay is most like a infinite bandwidth transmission line?
• Define metastability.
• When does metastability occur?
• Give one example of a situation where metastability could occur.
• Give two ways metastability could manifest itself in a state machine.
• What is MTBF?
• Does MTBF give the time until the next failure occurs?
• Give 3 ways in which to reduce the chance of metastable failure.
• Give 2 advantages of using a synchronous reset methodology.
• Give 2 disadvantages of using a synchronous reset methodology.
• Give 2 advantages of using an asynchronous reset methodology.
• Give 2 disadvantages of using an asynchronous reset methodology.
• What are the two most fundamental inputs (files) to the synthesis tool?
• What are two important steps in synthesis? What happens in those steps?
• What are the two major output (files) from the synthesis process?
• Name the fundamental 3 operating consitions that determine (globally) the delay characteristics of CMOS gates. For each how they affect gate delay?
• For a single gate, with global gating conditions held constant , what 3 delay coefficients effect total gate delay? Which is the most sensitive to circuit topology?

What is the difference between FPGA and CPLD?

• "A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations".

• This is what Wiki defines.....!!

• Granularity is the biggest difference between CPLD and FPGA.

• FPGA are "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories.FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available.

• CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.

• Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.

• The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

• Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA.

• FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this.

• FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500>

• Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment).

• Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue.

• Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families.

• Use FPGAs for larger and more complex designs.

• FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result.

What is the difference between FPGA and ASIC?

• This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.

• Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.

• Field Programable Gate Arrays

• Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!

• No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!

• Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

• More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

• Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

• FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC.

• Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.

• Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

• FPGA sythesis is much more easier than ASIC.

• In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

• Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

• You have to use the resources available in the FPGA. Thus FPGA limits the design size.

• Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

• Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

• Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

• In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

• In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

• Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

• Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)

• Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

• Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.

• Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.

• Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.

FPGA Interview Questions