Computer:  IC design. Device and process simulation. Scientific analytical and statistical tools. MS Office. Website design and Search engine optimization.

PROFESSIONAL EXPERIENCE:

         AMD, Sunnyvale, CA                                                                                    2005-2007

MTS, Technology Development Group.

·         Device and circuit reliability, on BULK and SOI technology generation from 90nm to 32nm. Reliability methodology development and technology qualification.

         LSI LOGIC, Milpitas, CA                                                                            1998-2005

Staff Engineer, Memory Technology and Process Integration.

·         SRAM core and related test structure design to ensure functionality, yield, and manufacturability. Develop and monitor inline process for SRAM integration on ASIC (from 0.35um-90nm technology generation).

         Ph. D RESEARCH, George Mason University, VA                                                    1994-1998

Ph.D. Candidate, SOI device physics and reliability.

·         Semiconductor device reliability studies and hot carrier degradations, esp. for SOI devices.

SINGAPORE TECHNOLOGY                                                                             1992

Process Engineer, Chartered Semiconductor Manufacturing

·         Process integration and semiconductor chip manufacturing of 0.8um VLSI technology

INSTITUTE OF SEMICONDUCTORS                                                              1987- 1992

Research Associate, Chinese Academy of Sciences, China

·         Physics of superconductor, III-V compound semiconductors and hetero-junctions.

 

PROFESSIONAL SKILLS:

Semiconductor Process and Reliability:

Process and memory technology integration, reliability qualification experiences starting from 0.35um to 32nm generation.

Designing and Testing:

·         Design and layout of transistors and circuits for characterization and reliability assessment. For SRAM manufacturability and design rule validation.

·         Transistor and circuit measurement for development, qualification and reliability on both wafer- and package-level, using both single-site and multi-site test system.

Computer /Equipment:

·         Agilent 4156 series and Keithley 4200 Pulse I-V for semiconductor device characterization. Celadon prober and Cascade probe station. Syntx RO test system for RO circuit reliability.

·         IC Layout design tools. Process monitoring tools (DataPower). Semiconductor simulation tools (process and device simulation).

·         Web page design tools, search engine optimization tools.

EDUCATION:

Ph.D., Electrical & Computer Engineering, George Mason University, GPA: 4.0.

Thesis: SOI device degradation and reliability study.

M.S., Electrical Engineering, Tsinghua University, Beijing, China, GPA: 3.2

Thesis: Research on VLSI processes

B.Sc., Electrical Engineering, Tsinghua University, Beijing, China, GPA: 3.3.

AWARDS AND HONORS:                1995, 1997 Fellowship in George Mason University

Publications

1.          Franklin Duan,  Stephen Cooper, Amit Marathe, John Zhang, Sankaran Kartik Jayanarayanan, “Impact of Monitoring Voltage on the Lifetime Extrapolation During the Accelerated Degradation Tests”, IIRW2006.

2.          Ramnath Venkatraman, Ruggero Castagnetti, Olga Kobozeva, Franklin L. Duan, Arvind Kamath, S.T. Sabbagh, Migual A. Vilchis-Cruz, Jhon Jhy Liaw, Jyh-Cheng You, and Subramanian Ramesh, "The Design, Analysis, and Development of Highly Measurable 6-T SRAM Bitcells for SoC Applications ", IEEE Transaction on Electron Devices, vol.52, No.2, February, 2005.

3.          F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, and S. Ramesh, LSI Logic Corporation, 2003, "Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability", ISQED'2003. pp119-124,

4.          W. Kong, R.Venkatraman, R. Castagnetti, F. Duan and S. Ramesh, "High-Density and High-Performance 6T-SRAM for System-on-Chip in 130 nm CMOS Technology", VLSI Symposium, 2001.

5.          Franklin L. Duan, Dimitris E. Ioannou, Shankar P. Sinha, and Frederick T. Brady,  “LDD Design Tradeoffs for Self Latch-Up and Hot Carrier Degradation Control in Accumulation Mode FD SOI MOSFET’s”, IEEE Transactions on Electron Devices, vol. 44, pp.972-977, 1997.

6.          F.L. Duan, X.Zhao, D.E. Ioannou, H.L. Hughes and S.T. Liu, “Detrimental Edge Effects on the Floating Body Phenomena in SOI MOSFETs”, Symposium of 192nd International Meeting of the Electrochemical Society, Inc., pp.239-245, 1997.

7.          Franklin L. Duan and Dimitris E. Ioannou, “Design and Analysis of a Novel Mixed Accumulation/Inversion Mode FD SOI MOSFET”, 1997 IEEE International SOI Conference Proceedings, pp.100-101, 1997.

8.          Franklin L. Duan, Dimitris E. Ioannou, Harold L. Hughes and Mike Liu, “Channel Coupling Imposed Tradeoffs Between Hot Carrier Degradation and Single Transistor Latch-Up in FD SOI MOSFET’s”, IEEE International Reliability Physics Symposium, pp.194-202, 1998.

9.          Dimitris E. Ioannou, Franklin  L. Duan, Shankar P. Sinha, and Andrej Zaleski, “Opposite-Channel-Based Injection (OCBI) of Hot-Carriers in SOI MOSFET’s: Physics and Applications”, IEEE Transaction on Electron Devices, vol.45, May 1998.

10.       D.E. Ioannou, F.L. Duan, and X. Zhao, “SIMOX Substrate and MOSFET’s for Enhanced Reliability and Performance”, 1997 International Semiconductor Device Research Symposium, pp.627-630, 1997.

11.       Dimitris E. Ioannou, Franklin L. Duan, Williams C. Jenkins, and Harold L. Hughes, “Channel Coupling Imposed Tradeoffs on Fully-Depleted (FD) SOI MOSFET’s”, submitted to ESSDREC’98.

12.       X. Zhao F.L. Duan, A. Thanailakis, D.E. Ioannou, R.K. Lawrence, and H.L. Hughes, “Hole Trap Investigation in Supplemental Oxygen SIMOX Wafers by Opposite Channel Based Charge Injection”, 1997 IEEE International SOI Conference Proceedings, pp.116-117, 1997.

13.       Shankar P. Sinha, Franklin L. Duan, Dimitris E. Ioannou, William C. Jenkins, and Harold L. Hughes, “Time Dependence Power Laws of Hot Carrier Degradation in SOI MOSFET’s”, 1996 IEEE International SOI Conference Proceedings, pp.18-19, 1996.

14.       S. P. Sinha, F.L. Duan, D.E. Ioannou, William C. Jenkins, Harold L. Hughes, and M.S. Liu, “Hot Carrier Degradation of Fully Depleted SIMOX MOSFET’s”, Proceedings of the 7th International Symposium On Silicon-On-Insulator Technology and Devices, pp.324-329, 1996.

Patents:

1.        Reduced soft error rate (SER) construction for integrated circuit structures, 2002

2.        Single channel four transistor SRAM, 2002

3.        A new method to detect random and systematic transistor degradation for transistor reliability evaluation in high-density memory – 2003

4.        Method and apparatus for characterizing shared contacts in high-density SRAM cell design – 2003

5.        New methodology to measure many more transistors on the same test area – 2007