technology + process

Is it a mac laptop? Cause if it is it would be shift+command+3.

65nm node technology = IBM CGS 11S

　

saved as a mhtml file

　

　

　

　

　

　

　

　

　

http://www3.ntu.edu.sg/ EE4613 - CMOS Process & Device Simulation

http://www.cse.psu.edu/research/mdl/mji/mjicourses Penn state UNiv VLSI Systems Design

 http://www3.ntu.edu.sg/eee/eee6/LectureNotes/E425/index.htm

http://www3.ntu.edu.sg/eee/eee6/LectureNotes/ 

　

trench

　

stress engineering

sigma shaped pMOS

　

　

retrograde well, Channel engineering techniques

Typically, channel engineering techniques, an effective method to improve device
performance, is accomplished by implants, which can also impact local sidewall doping. In this
section, different implants used to increase device performance are presented.

　

　

ldd is after the n+p+

etching

　

　

Spacer

Yield

　

ellipsometry

　

　

　

　

litho

`to reduce wmin,

　

duv 35nm ebeam 5nm nano patterning 10 - 20 nm

　

　

　

　

Contacts

　

　

resistence (contact, sheet, metal

Silicon

n+ p+ Si 1000 uohm cm

Silicide

TiSi 10–15uohm cm 750–900 oC

CoSi 18uohm cm Co 550–900 oC

NiSi 20uohm cm Ni 350–750 oC

Metal

AL 2.7 uOhm cm

Cu 1.7 uOhm cm

　

pure silicon 20 -100 ohm / sqare

silicon + silicode 1 - 4 ohm / sqare

Contact R = 5 - 20 ohm metal to n+p+ or poly

Contact R = 1 - 5 ohm metal to metal

4000A thickness = 4e-5 cm

CU/t = 3e-6/4e-5 = 0.1 ohm / sqare

　

http://ecee.colorado.edu/~bart/book/mobility.htm

http://www.ioffe.ru/SVA/NSM/Semicond/Si/electric.html

 

　

Salicide, silicide

　

　

　

　

　

　

　

Cu Copper low K

　

　

reduce EM: Cu better, no 90 degree corner bend, wider metal, multi via, Electromigration-aware design

Interconnect

low k

2 properties: adhesiveness, mechanical-thermal strength, need buffer layer btw Cu and Low K

semiconductor process http://en.wikipedia.org/wiki/Semiconductor_device_fabrication

ductor process

　

　

E3-327: Nanoelectronics Device Fabrication and Characterization