SRAM

http://larc.ee.nthu.edu.tw/~dtc/doc/940603.pdf

Each SRAM has two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. An SRAM cell has three different states. It can be in: standby (the circuit is idle), reading (the data has been requested) and writing (updating the contents). The SRAM to operate in read mode and write mode should have "readability" and "write stability" respectively. SRAM is more expensive, but faster and significantly less power hungry (especially idle) than DRAM.

1.2 SRAM Designs IBM2005
All SRAM arrays in this technology must utilize dummy edge cells around the external perimeter of the
array. Any exception to this must be approved by the waiver review board. Additionally, All SRAMS
designed for this technology MUST have body contacts on the sense amplifier input nFETs. See section
3.15, “Body Contact Rules” on page 123.
Two cell layout are in review and under development. Both cells are M1-bitline/M2-wordline design. The first
cell is 1.3mm x 0.5mm (0.65 mm2) in design dimension. The second cell is 1.5mm x 0.5mm (0.75 mm2) in design
dimension.

a very good article of SRAM theory

http://www.iis.ee.ethz.ch/~kgf/aries/5.html#5.4  saved as 222hs.mhtml

*sram
　

http://www.southalabama.edu/engineering/ece/faculty/sruss/EE%20534/Lecture%2013.pdf

2K word = 2x2~10

64K=2~16, 64K = 256 x 256 =2~8 x 2~8 1M = 2~20

TBL to reduce bit-line coupling noise

SRAM cell

Silicon lab in Austin http://www.silabs.com/about/careers/Pages/search.aspx

Layout

SNM The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

example: NML is input start from low, where is the value cause the upset of the out put, in the vo-vin chart, start vin from lower side till the slope =1, NML=@slope1 - low (0v) = 2.3v; NMH the input start from high, where is the value to cause the upset of the output, start vin from vdd till slope is 1, NMH = high (vdd) - slope@1 = 1.7v

more:http://www.ece.unm.edu/~jimp/vlsi/slides/chap2_1.html 

SRAM theory Iread, cell current, butterfly curve, sram snm, Iwrite

These access
transistors are designed to be strong enough to overcome the positive feedback in the bitcell
core and overwrite the contents of the bitcell. On the other hand, they also need to be weak
enough that the content of the bitcell is not accidentally disturbed during a read operation.
Herein lies one of the fundamental constraints in SRAM bitcell design - the tradeoff between
read and write margin. The cross-coupled inverting gain elements in the core are usually
implemented as two static CMOS inverters with each static CMOS inverter consisting of a
PMOS and NMOS transistor. This SRAM bitcell design is usually called a 6T bitcell due
to the fact that there are 6 transistors in a bitcell.

1.2.1 SRAM Margins
SRAM margins are used to quantify the robustness of a read and write operation. 1.3
(a) illustrates the schematic of a bitcell set up for SRAM static margin extraction. A
voltage source is connected to one of the internal nodes (CL). This node voltage is swept
while measuring voltages at other nodes or the current flowing out of this voltage source
(IN−Curve). Figure 1.3 (b) plots the technique for characterizing the static noise margin
(SNM) of a bitcell [61]. Both bit-lines and the word-line (BL, BL, WL) are connected to
VDD. The first curve is measured by sweeping the voltage of node CL while monitoring
the voltage at node CH. This essentially traces the switching characteristic of one of the
cross-coupled inverters. The other curve is measured by sweeping node CH while monitoring
the voltage at node CL. The static noise margin for storing a 0 or 1 (SNM0 and SNM1)
corresponds to the side of the largest square that fits into the respective lobes. This static
margin essentially characterizes the largest voltage perturbation that can be sustained in
the internal nodes of the bitcell before the bitcell looses the ability to store two states. The
bias conditions applied on the bitcell for write margin characterization depend on the data
that is being written into the bitcell. To write a logic-0 into node CL, node BL is grounded
while nodes BL and WL are connected to VDD. The voltage at node CL is then swept from
VDD to ground while the current flowing through the voltage source (IN−Curve) is monitored.
This emulates the bias conditions applied to the transistors as a logic-0 is written to node
CL. IN−Curve observed during this voltage sweep is plotted on Figure 1.3 (c). The static
write margin(Iwrite) is defined as the minimum current observed at the right side of the plot
[13]. The Iwrite write margin is preferred over an alternative write noise margin proposed by
Seevinck et al. because of easier extraction from experimental results and better correlation
with SRAM write Vmin across a wide range of voltages [24].

understand writing ability in sram PG cuurent must > PU current, (imagine PU current is very high, Iw is negative ...

understand writing ability in sram PG cuurent must > PU current, (imagine PU current is very high, Iw is negative ...

The write N-curve illustrated in Fig. 1.2(b) is obtained by sweeping the voltage at the
storage node QR (QL), with BL (BL) and WL biased at VDD and BL (BL) biased at GND,
and monitoring the current sourced into the storage node. The write-ability current [8, 9],
Iw, is defined as the minimum current past the inverter PUL-PDL trip point, and is a measure
of the difference between PGR and PUR currents.

SNM is the
maximum tolerable DC noise voltage at a storage node that does not cause a read
disturbance, and it is the length of the side of the largest square that can fit into the “eyes”
of the butterfly curves, i.e., the read voltage transfer characteristics (VTC), for the SRAM
cell.

CAM cell

nor, nand flash, e2prom, eprom, rom

Code Netlist

.temp 70
vdd 1 0 dc 1v
m1 3 2 1 1 pmos w=115n l=65n
m2 3 2 0 0 nmos w=130n l=65n
m3 2 3 1 1 pmos w=115n l=65n
m4 2 3 0 0 nmos w=130n l=65n
m5 4 5 3 0 nmos w=100n l=75n
m6 6 5 2 0 nmos w=100n l=75n
.include'/home/student1/65nm_bulk.txt'
vbl 4 0 dc 1v
vblr 6 0 dc 1v
vwl 5 0 dc 1v
vnode 2 0 dc 0v
c1 3 0 10ff ic=1
c2 2 0 10ff ic=0
.dc vnode 0v 1v .2v
.probe dc v(3) v(2)
.option post probe
.end