MOSFET

http://www3.ntu.edu.sg/ EE4613 - CMOS Process & Device Simulation http://www3.ntu.edu.sg/eee/eee6/LectureNotes/
http://www.cse.psu.edu/research/mdl/mji/mjicourses Penn state UNiv VLSI Systems Design http://www.cse.psu.edu/research/mdl/mji/mjicourses/477
ESD http://www-tcad.stanford.edu/tcad/pubs/device/
http://ece.iisc.ernet.in/~navakant/nano/2007/course.html
CADENCE MANUAL http://www.seas.upenn.edu/~ese570/manual_1.htm http://www.seas.upenn.edu/~ese570/
file with star*
http://www.22ic.cn/ 中国微电子网微电子论坛【微电子百科】微电子家园微电子微博客
PPTSlideWorld http://pptslideworld.com/find?search=semiconductor+technology&page=1&type=ppt&cat=216

Is it a mac laptop? Cause if it is it would be shift+command+3.

GIDL

Mostfet knowledge

ecee.colorado.edu

device mosfet

http://www3.ntu.edu.sg/eee/eee6/LectureNotes/E425/index.htm

Sah equation http://cnx.org/content/m1024/latest/

This equation is called the Sah Equation after C.T. Sah, who first described the MOS transistor operation this
way back in 1964. It is very important because it describes the basic behavior of the MOS transistor.

Cox and Cj in fF are close, Cox=0.5- 0.7fF, Csd = 0.45fF

Finfet, 3d, statistical of mosfet

NA=1e18cm-3, - > there are 8 NA in (20x20x20nm)3 volume, finfet add W to 20x3 24 NA , lattice space 2A, 20nm -> 100 atoms. In 20nm square, change 1 atom, 1/8 change, in 90nm range, 90nm cube 9^3 times NA = 300 NA 1 atom change, 1/300

short channel effect SCE, Vt roll off, doping, sti edge (thin ox mosfet),sti stress (compressive), reverse narrow cchannel effect, lod

stress engineering tpen cpen SiGe

Vt roll off with channel width

STI affects the mechanical state and electrical performance of neighboring transistors, motivating the need to analyze and model its impact during technology development and design. This article presented TCAD simulations of two such prominent cases: the narrow-width effect and stress proximity effects. In the narrow-width effect, STI contributes to variation of the channel doping and stress, with the combined result of a significant shift in the threshold voltage. Stress proximity effects are endemic to strained silicon technologies. The STI adds compressive stress to its adjacent silicon regions, and is summed with other stress sources to determine the overall stress state and electrical performance of individual transistors in the design.

Q1为一垂直式PNP BJT, 基极(base)是nwell, 基极到集电极(collector)的增益可达数百倍；Q2是一侧面式的NPN BJT，基极为P substrate，到集电极的增益可达数十倍；Rwell是nwell的寄生电阻；Rsub是substrate电阻。
以上四元件构成可控硅（SCR）电路，当无外界干扰未引起触发时，两个BJT处于截止状态，集电极电流是C-B的反向漏电流构成，电流增益非常小，此时Latch up不会产生。当其中一个BJT的集电极电流受外
部干扰突然增加到一定值时，会反馈至另一个BJT，从而使两个BJT因触发而导通，VDD至GND（VSS）间
形成低抗通路，Latch up由此而产生。
产生Latch up 的具体原因
• 芯片一开始工作时VDD变化导致nwell和P substrate间寄生电容中产生足够的电流，当VDD变化率大到一定地步，将会引起Latch up。
• 当I/O的信号变化超出VDD-GND（VSS）的范围时，有大电流在芯片中产生，也会导致SCR的触发。
• ESD静电加压，可能会从保护电路中引入少量带电载子到well或substrate中，也会引起SCR的触发。
• 当很多的驱动器同时动作，负载过大使power和gnd突然变化，也有可能打开SCR的一个BJT。
• Well 侧面漏电流过大。
防止Latch up 的方法
• 在基体（substrate)上改变金属的掺杂，降低BJT的增益
• 避免source和drain的正向偏压
• 增加一个轻掺杂的layer在重掺杂的基体上，阻止侧面电流从垂直BJT到低阻基体上的通路
• 使用Guard ring: P+ ring环绕nmos并接GND；N+ ring环绕pmos 并接VDD，一方面可以降低Rwell和Rsub的阻值，另一方面可阻止栽子到达BJT的基极。如果可能，可再增加两圈ring。
• Substrate contact和well contact应尽量靠近source,以降低Rwell和Rsub的阻值。
• 使nmos尽量靠近GND，pmos尽量靠近VDD,保持足够的距离在pmos 和nmos之间以降低引发SCR的可能
• 除在I/O处需采取防Latch up的措施外，凡接I/O的内部mos 也应圈guard ring。
• I/O处尽量不使用pmos(nwell)

ESD

ESD resources http://www-tcad.stanford.edu/tcad/pubs/device/

SB MOSFET (+SOI)

http://www3.ntu.edu.sg/ EE4613 - CMOS Process & Device Simulation

http://www.cse.psu.edu/research/mdl/mji/mjicourses Penn state UNiv VLSI Systems Design