SRAM

http://larc.ee.nthu.edu.tw/~dtc/doc/940603.pdf

http://www.southalabama.edu/engineering/ece/faculty/sruss/EE%20534/Lecture%2013.pdf

2K word = 2x2~10

64K=2~16, 64K = 256 x 256 =2~8 x 2~8 1M = 2~20

TBL to reduce bit-line coupling noise

SRAM cell

Silicon lab in Austin http://www.silabs.com/about/careers/Pages/search.aspx

SNM The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.

example: NML is input start from low, where is the value cause the upset of the out put, in the vo-vin chart, start vin from lower side till the slope =1, NML=@slope1 - low (0v) = 2.3v; NMH the input start from high, where is the value to cause the upset of the output, start vin from vdd till slope is 1, NMH = high (vdd) - slope@1 = 1.7v

more:http://www.ece.unm.edu/~jimp/vlsi/slides/chap2_1.html 

nor, nand flash, e2prom, eprom, rom

*sram
　

Code Netlist

.temp 70
vdd 1 0 dc 1v
m1 3 2 1 1 pmos w=115n l=65n
m2 3 2 0 0 nmos w=130n l=65n
m3 2 3 1 1 pmos w=115n l=65n
m4 2 3 0 0 nmos w=130n l=65n
m5 4 5 3 0 nmos w=100n l=75n
m6 6 5 2 0 nmos w=100n l=75n
.include'/home/student1/65nm_bulk.txt'
vbl 4 0 dc 1v
vblr 6 0 dc 1v
vwl 5 0 dc 1v
vnode 2 0 dc 0v
c1 3 0 10ff ic=1
c2 2 0 10ff ic=0
.dc vnode 0v 1v .2v
.probe dc v(3) v(2)
.option post probe
.end