High K metal gate learning

gate dielectrics

Several gate dielectrics have been explored: Hafnium oxide, HfSiO and HfSiON. Each of these has its own tradeoffs. HfSiO has a lower k value than Hafnium oxide, but could provide higher crystallization temperature and higher mobility. Additional N incorporation into HfSiO could provide increased thermal stability and improve effective k value, but reduces mobility. To get the highest k film for a Gate-Last process, Dr. Bob should probably go with Hafnium oxide – interfacial silicon oxide and HfSiO form during the Hafnium Oxide deposition anyway, which helps with mobility issues.
　

Hf-based high-k films (like HfSiO and HfO2) 　
near-midgap nitrided metals like TiN or TaN are arguably among the most common materials considered today.
The gate-first approach was initially developed by Sematech and the IBM-led Fishkill Alliance. It relies on very thin capping layers — Al2O3 for the PMOS and LaOx for the NMOS transistors — to create dipoles that set the threshold voltage of the device. However, thermal instabilities in HK/MG devices were reported and can lead to threshold voltage shifts and re-growth in the gate stack. This issue is particularly acute for pMOS at scaled EOT,
The second way of integrating HK/MG, with a so-called gate-last process, was initially developed by Intel, implementing it in its 45nm technology [1]. In that iteration, the hafnium dielectric was deposited early on in the flow, prior to a sacrificial polysilicon gate was created. After the high-temperature S-D and silicide annealing cycles, the dummy gate was removed and metal gate electrodes were deposited last. More recently, Intel introduced in their 32nm technology a slightly different scheme where the high-k is deposited last, right before the metal gate electrodes, and after the complete removal of the dummy gates. One possible advantage with this new approach is to improve the device reliability and mobility at scaled EOT, which can be significantly degraded when the high-k dielectric has gone through the high thermal steps of the flow, just like in the gate-first approach case [8].
Recently, UMC disclosed a hybrid approach to integrate HK/MG, combining both gate-first (for nMOS) and gate-last (for pMOS) [9]. This allows the tackling of one of the main challenges of gate-first when targeting high-performance applications, which is the high pMOS VT at scaled EOT, while avoiding the full, complex CMOS gate-last integration that requires multiple CMP steps and dual metal gate deposition.
restricted design rules (RDRs), like the 1-D design approach (where gates are all aligned in a given direction). However, at the 28nm node, and more so at the 22nm node, this layout restriction is becoming mainstream anyway, due to lithography constraints. Therefore, the higher design flexibility of gate-first might fade away for the future nodes, as more and more RDRs will need to be implemented.

EOT target = 1.2nm

Metal Gate Materials

Companies use TiN, TiAlN, TiSiN, TaN, TaAlN, TaSiN. Work functions of these materials can be tuned by changing the percentage of different elements in the compound and also by adding cap layers. Dr. Bob should play with these different materials smartly and tune work function based on his requirements.

Intels high k metal gate data

Gate metarial

gate first gate last

Integrating high-k /metal gates: gate-first or gate-last?

gate firs or gate last Why is High-k/Metal Gate so Hard?

Phonon scattering

Cheminghu intro

REDUCTION gate dielectric remains a major challenge for
scaling CMOS technology beyond the 100-nm node.

The use of high- K will allow a significant reduction of the
equivalent oxide thickness of the gate dielectric itself. However,
there are additional factors such as polysilicon-depletion effect
(PDE) contributing to the total CET of gate dielectrics[1].
Replacing the polysilicon gate with a metal gate will essentially
eliminate gate depletion and consequently reduce the CET by
several angstroms. In addition, polysilicon gates are thermodynamically
unstable on many high- materials, such as
[2] and [3], while many metals are expected to be stable
on advanced gate dielectrics.
A major advantage of polysilicon gates is that by doping
polysilicon with either acceptor or donor atoms one can change
the work function of the gate electrode and thus achieve surface-
channel bulk-Si p-MOSFET and n-MOSFET devices with
the desirable Vt. Since there is no well-established
way to modify the work function of a metal, two different
metals (one with a high work function of around 5 eV and the
other with a low work function of around 4 eV) will likely be
needed for future bulk CMOS devices. A straightforward way to
implement a dual-work-function metal gate CMOS technology
[4] is as follows. After blanket deposition, the first metal is removed
from either the p-MOS or n-MOS regions, and then a
second metal with a different work function is deposited. Unfortunately,
this entails exposing the gate dielectric to the metal
etchant, which causes undesirable thinning and potential dielectric
reliability problems.
We propose an alternative approach in which dual work function
gates can be fabricated without exposing the gate dielectric
to the etchant. First, deposit a thin layer of one of the metals
over the entire wafer. For the sake of discussion, let us assume
this first metal is the one with the low work function. Then
deposit the second (high work function) metal over the entire
wafer (Fig. 1(a)). Next, selectively remove the high work function
metal from the n-MOS regions while the p-MOS regions
are protected by photoresist. Since the low work function metal
is the only metal remaining on top of the n-MOS dielectric, it
will clearly determine the n-MOSFET threshold voltage .
The two remaining metals on the p-MOS side are subsequently
allowed to interdiffuse. In some cases, the two metals will mix,
yielding an intermediate gate work function. By choosing a suitable
thickness combination for the metal layers, the composition
of the mixture and thus the gate work function can be controlled.
This approach would allow for a continuous tuning of transistor
threshold voltages independent of substrate doping concentration.
This can be especially important for ultra-thin body MOS
transistors [5], where adjustment of the substrate doping is not
an effective way of -control. In other cases, one of which we