FPGA PLD CPLD

62) What is a SoC (System On Chip) , ASIC, "full custom chip", and an FPGA?

Two other interpretations of SoC are 1) a chip that integrates various IP (Intellectual Property) blocks on it and is thus highly centered with issues like Reuse, and 2) a chip integrating multiple classes of electronic circuitry such as Digital CMOS, mixed-signal digital and analog e.g. sensors, modulators, A/Ds, DRAM memory, high voltage power, etc.

ASIC stands for "Application Specific Integrated Circuit". A chip designed for a specific application. Usually, I think people associate ASICs with the Standard Cell design methodology. Standard Cell design and the typical "ASIC flow" usually means that designers are using Hardware Description Languages, Synthesis and a library of primitive cells (e.g. libraries containing AND, NAND, OR, NOR, NOT, FLIP-FLOP, LATCH, ADDER, BUFFER, PAD cells that are wired together (real libraries are not this simple, but you get the idea... Design usually is NOT done at a transistor level. There is a high reliance on automated tools because the assumption is that the chip is being made for a SPECIFIC APPLICATION where time is of the essence. But, the chip is manufactured from scratch in that no pre-made circuitry is being programmed or reused. ASIC designer may, or may not, even be aware of the locations of various pieces of circuitry on the chip since the tools do much of the construction, placement and wiring of all the little pieces.

Full Custom, in contrast to ASIC (or Standard Cell), means that every geometric feature going onto the chip being designed (think of those pretty chip pictures we have all seen) is controlled, more or less, by the human design. Automated tools are certainly used to wire up different parts of the circuit and maybe even manipulate (repeat, rotate, etc.)sections of the chip. But, the human designer is actively engaged with the physical features of the circuitry. Higher human crafting and less reliance on standard cells takes more time and implies higher NRE costs, but lowers RE costs for standard parts like memories, processors, uarts, etc.

FPGAs, or Field Programmable Gate Arrays are completely designed chips that designers load a programming pattern into to achieve a specific digital function. A bit pattern (almost like a software program) is loaded into the already manufactured device which essentially interconnects lots of available gates to meet the designers purposes. FPGAs are sometimes thought of as a "Sea of Gates" where the designer specifies how they are connected. FPGA designers often use many of the same tools that ASIC designers use, even though the FPGA is inherently more flexible. All these things can be intermixed in hybrid sorts of ways. For example, FPGAs are now available that have microprocessor embedded within them which were designed in a full custom manner, all of which now demands "SoC" types of HW/SW integration skills from the designer.

Mixed-signal RF/wireless, A/Ds,

Wireless Technology

Radio frequency (RF) and analog mixed-signal (AMS) technologies which serve the rapidly growing wireless communication market represent essential technologies in the semiconductor space. RF/AMS circuits convert input radio signals into digital data which can be passed to a baseband processor for data processing. This type of conversion enables the functionality of cell phones and other wireless devices.

DSP数字信号处理(Digital Signal Processing，简称DSP)

DSP（digital singnal processor）是一种独特的微处理器。其工作原理是接收模拟信号，转换为0或1的数字信号，再对数字信号进行修改、删除、强化。 

What is the difference between FPGA and CPLD?

• FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once.

• The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.

• Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA.

• FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this.

• FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500>

• Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment).

• Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue.

• Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families.

• Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage.

• Use FPGAs for larger and more complex designs.

• FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result.

What is the difference between FPGA and ASIC?

• Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs.

• Field Programable Gate Arrays

• Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !!

• No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!!

• Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis.

• More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device.

• Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features.

• Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically.

• Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

• FPGA sythesis is much more easier than ASIC.

• In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

• Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race !

• You have to use the resources available in the FPGA. Thus FPGA limits the design size.

• Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation.

• Application Specific Intergrated Circiut

• Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA.

• Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations.

• Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !!

• In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.

• In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) .

• Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC.

• Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!)

• Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE.

• Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer.

• Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity.

• Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.

http://v.youku.com/v_show/id_XOTcxMDc2NjQ=.html

fpga + non - volatile memory

use anifuse, no technology dependent (can be 28nm, 4M of space for 4K of booting info, 1000 times of writing)

http://www.kilopass.com/comparing-anti-fuse-non-volatile-memory-in-28nm-high-k-metal-gate-with-other-nvm-solutions/