[6] J. Khare et al, “SRAM-based Extraction
Characteristics,” Proc. of Int’l Conf.
Structures, 1994, pp. 98-107.

During external testing, a test response can be collected to
generate a memory bitmap (Bitmaping is a vehicle of diagnosis
in which each bitmap displays the location and behavior
of the failing memory cells of a memory array). For
manufacturing feedback, the bitmap may be classified into
different fail patterns. Using results from failure analysis or
fabrication simulation, a dictionary can be created mapping
the fail patterns to defects, which is a very powerful manufacturing
process monitoring tool. For example, when a
yield problem occurs, the observed fail patterns may help to
narrow down the suspected manufacturing steps.[6]

Several example of monochrome (the white area represents
good cells and black squares represent failing cells) bitmap
patterns are shown in Fig. 2: Aside from a single,
failing cell (a), the failing cell may form a cluster (also
shown in a). The failing cells may also form a column (b) or
a row (c). Further, part of a row (or column) may be failing
(d), and a combination of a column and a row of failing cells
may also occur (e). Finally, two rows (or columns) may fail
as shown in (f).

from: 
Enabling Embedded Memory Diagnosis via Test Response Compression
John T Chen Janusz Rajski* Jitendra Khare**1 Omar Kebichi* Wojciech Maly
Carnegie Mellon University - Department of ECE
jtchen@ece.cmu.edu
*Mentor Graphics Corporation - Design for Test Group
**Intel Corporation - Sacramento - DFT/DFM Group

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Structured ASICs offer a cost-effective solution for the mid-volume
ASIC design with 75% less development costs than cell-based ASICs
and unit costs up-to 90% less than complex FPGAs. (See Figure #2)
In this article I will present a new design paradigm that has come of
age, the structured ASIC.

from: 
Structured ASIC Design: A New Design
Paradigm beyond ASIC, FPGA AND SoC
Dr. Danny Rittman
August 2004

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Pattern Sensitive and ElectricalMemory Test

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In SRAM design, the Data Retention Voltage (DRV) defines
the minimum VDD under which the data in a memory
unit is still preserved. An analytical model of DRV is developed
to investigate the dependence of DRV on process and
design parameters (Section 2). To verify the new model and
further understand the limitations of DRV under realistic
conditions, a 4KB SRAM test chip with dual-rail supply
scheme was designed and fabricated in a 0.13µm technology,
as introduced in Section 3. This scheme targets ultra
low-power applications and uses a customized on-chip switch
capacitor converter to generate standby VDD. Section 4 presents
measurement results of the SRAM data preservation
and leakage suppression. Impact of various process and design
factors on DRV is analyzed in Section 5. Finally, Section
6 concludes current work and proposes future directions.

from: 
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, and Jan Rabaey
Department of EECS, University of California at Berkeley, Berkeley, CA 94720, USA

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A schematic of the test and I/V traces are shown in figures 1 and 2. 

But perhaps the most useful design for FA feature is an analogue mode in which the bit line pairs can be accessed through the data lines without the involvement of the sense amps, I/O drivers, or pre driver circuits. 

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12. 什么分数才算好？ 
credit score一般在350-850之间。 
在申请贷款的时候，分数高有利于拿到最好的offer。 
通常650以上房贷就没有问题，720以上可以拿到最好的车贷。


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