Introduction

As the semiconductor industry transitions from aluminum to copper interconnects, the Chemical Mechanical Planarization (CMP) process is being redefined. In traditional aluminum processing, excess SiO2 interlevel dielectric (ILD) overcoats the preformed (plasma etched) aluminum interconnect “wires”, so CMP does not reduce aluminum line thickness. In the copper dual-damascene process, CMP removes excess electrochemically deposited (ECD) copper, forming the interconnect wires and interlevel vias. CMP provides the planarity necessary for the subsequent level of via/interconnect structures, but, if not adequately controlled, may thin the copper lines. The copper dual-damascene process requires CMP to polish three different materials, the ECD copper, the Ta, TaN, or other barrier material, and the ILD (or low-k ILD). Because each of these materials has different hardness and chemistry, they have different polishing rates. Developing the appropriate pads and slurry mixes to correctly process all three materials and maintaining the desired polishing rates during high volume manufacturing is a significant challenge. Metrology tools that can precisely characterize and monitor the copper CMP process on product wafers at semiconductor production throughput rates will be an important requirement for manufacturers making copper interconnect devices.

Background

Because copper can not be etched directly, the dual-damascene process is being used for copper interconnect manufacturing. In dual-damascene, both vias and trenches are etched into the ILD. A thin barrier layer and a copper seed layer are then deposited over the etched ILD. Next, ECD copper is used to fill the vias and trenches until a thick copper blanket covers the entire surface of the wafer. CMP then polishes the wafer, ideally stopping just after the barrier layer is cleared in all areas (and over all types of structures) across the wafer, isolating the copper wires in their ILD trenches. Determining the exact end point for the CMP process can be difficult. A main reason for this is different structures polish at different rates. Figure 1 shows several of the common problems encountered in copper dual damascene CMP processing. Dishing occurs when large copper lines and pads polish more quickly in the soft copper center than on the harder barrier/ILD edge. Dishing can thin the wire or pad, causing higher resistance wires or low-reliability bond pads. Erosion occurs when narrow arrays of copper and ILD polish more quickly than non-patterned areas, thinning wires and increasing their resistance. Erosion can also result in a sub-planar dip on the wafer surface. When the subsequent layer of interconnect is completed, a shallow “pool” of copper can fill this dip, causing short-circuits between adjacent wires. Copper or barrier residue caused by CMP underpolishing can also short circuit the interconnect lines and cause device failure. To prevent this possibility, most wafers are slightly overpolished. However, severe overpolishing can thin the copper lines, both increasing circuit resistance and the possibility of pooling on the next layer. Therefore, to maintain high production yields, the CMP process must be locally monitored on various test structures. These will indicate whether the polishing process remains within the desired parameters on structures of differing patterns and densities, and whether the copper, barrier, and ILD are locally polishing exactly as required. While a generalized large-spot in-situ CMP endpoint detector will help control the CMP process in production, small spot, localized monitoring will also be required in order to maintain high yield and to catch mis-processing early.

Figure 1. Common CMP mis-processing problems result from the different polishing rates of copper, barrier, and ILD.