http://www.ece.cmu.edu/~ee762/hspice-docs/html/hspice_and_qrg/index.html

Readings and Knowledge on semiconductor and IC

All Handouts are available in the file cabinet in 3rd floor of Gates
Handouts do not stay in the file cabinet very long. Please don't wait.

Lecture	2 slides/page	extra
Lecture 1 - Overview/Modelling	2up-pdf
Lecture 2 - Wires and Wire Models	2up-pdf	updated
Lecture 3 - Transistor Modelling	2up-pdf
Lecture 4 - Adders	2up-pdf
Lecture 5 - Other Adder Issues	2up-pdf
Lecture 6 - Transistor in the real model	2up-pdf
Lecture 7 - Flop and Latch Design	2up_pdf
Lecture 8 – Clocking of High Performance Processors	2up_pdf
Lecture 9 - Skew Tolerant Design	2up_pdf
Lecture 10 – Circuit Rules of Thumb	2up_pdf
Lecture 11 – Asynchronous Circuits	2up_pdf
Lecture 12 – VLSI Power Delivery	2up_pdf
Lecture 14 – Test and Debug	2up_pdf
Lecture 15 – Processing and Reliability Issues	2up_pdf
Lecture 16 – Overview of High-Speed IOs	2up_pdf
Lecture 17 – Power in CMOS VLSI	2up_pdf

Reading :

Wires

Timing Models (Horowitz 84)

Line-To-Ground Capacitance Calculation (Barke 88)

Cap Extraction (Arora 96)

Transistors

Transistor Matching (Pelgrom 89)

Transistor Matching (Lovett 98)

High-Field MOS Model (Chen 97)

Circuits

Logical Effort Review (Harris)

Logical Effort Revisited

Signal and Power Integrity (Lev96)

Dynamic Logic and Latches (Gronowski96)

Clocking

Alpha Clocking (Baily98)

Skew Tolerant Domino (Harris97)

Latch Comparison (Stojanovic99)

Clocking Slides from EE271 (1up PDF)

Statistical Clock Skew Modeling with delay variation (Harris and Naffziger 01)

Adder

Adder Paper (Naffziger96)

Adder Slides (Naffziger96)

Adder Slides from EE271 (1up PDF) and (2up PS)

Interconnects

Low-swing Onchip Signaling (Zhang2000)

Efficient On-Chip Global Interconnects (RonHo2003)

CAMs

First DRAM CAM (Mundy72) (fun only to see what circuit design was like back then)

Large CAM for IP lookup (Sharfi98)

DRAM CAM (Yamagata92)

EEPROM CAM (Miwa96)

Preclassification CAM (Schultz96)

Handout #	Content	Files	Date published / revised
1	Information Sheet	pdf	9/17/04
2	L1: Introduction, Long Channel MOS Model	1 pp, 2 pp	9/19/04
3	L2: Common Source Amplifier	1 pp, 2 pp	9/19/04
4	Homework 1 (due 10/04/04)	pdf	9/27/04
5	L3: Figures of Merit for Transistors	1 pp, 2 pp	9/27/04
6	L4: Subthreshold Operation, Short Channel Effects	1 pp, 2 pp	9/29/04 / 10/08/04
7	Homework 2 (due 10/11/04)	pdf	10/04/04
8	L5: g_m/I_D Design Methodology	1 pp, 2 pp	10/01/04
9	L6: Extrinsic Capacitances	1 pp, 2 pp	10/04/04
10	L7: Zero Value Time Constant Analysis	1 pp, 2 pp	10/05/04
11	Homework 3 (due 10/18/04)	pdf	10/11/04
12	L8: Body Effect, Common Gate Stage	1 pp, 2 pp	10/08/04/ 10/13/04
13	L9: Common Drain Stage	1 pp, 2 pp	10/11/04
14	L10: Differential Pair	1 pp, 2 pp	10/13/04/ 10/21/04
15	Homework 4 (due 10/25/04)	pdf	10/17/04
16	L11: Offset Voltage, Current Mirrors	1 pp, 2 pp	10/16/04
17	L12: Process Variations, Feedback	1 pp, 2 pp	10/18/04
18	L13: Fully Differential Amplifiers	1 pp, 2 pp	10/20/04
19	Homework 5 (due 11/01/04)	pdf	10/25/04
20	L14: Stability, Feedback Circuit Analysis	1 pp, 2 pp	10/23/04
21	L15: Loop Gain Simulation	1 pp, 2 pp	10/25/04
22	L16: Two-Stage OTA	1 pp, 2 pp	10/27/04
23	Project (due 11/24/04)	pdf	11/01/04
24	Project Submission Template	txt	11/01/04/ 11/09/04
25	L17: Compensation, Two-Stage OTA Design	1 pp, 2 pp	10/30/04/ 11/22/04
26	L18: Feedback and Port Impedances	1 pp, 2 pp	11/01/04
27	L19: Step Response	1 pp, 2 pp	11/03/04
28	L20: Slewing	1 pp, 2 pp	11/06/04/ 12/04/04
29	L21: OTA Variants, CMFB implementation	1 pp, 2 pp	11/06/04
30	L22: Single Ended OTAs, Output Stages	1 pp, 2 pp	11/12/04
31	L23: Electronic Noise	1 pp, 2 pp	11/15/04/ 11/22/04
32	L24: kT/C Noise	1 pp, 2 pp	11/18/04/ 11/22/04
33	L25: Supply Independent Biasing	1 pp, 2 pp	11/19/04/ 12/09/04
34	L26: Bandgap Reference	1 pp, 2 pp	11/23/04
35	L27: Bandgap Reference	1 pp, 2 pp	11/24/04/ 11/29/04
36	L28: Technology Scaling	1 pp, 2 pp	11/29/04
37	L29: Class summary, Project Presentations	1 pp, 2 pp	11/30/04

EE311:

Class Notes
Handout 1. Same as the course info on this web page
Handout 2. Trends in Integrated Circuits Technology
Handout 3. MOS Gate Dielectric Technology
Handout 4. Shallow Junctions
Handout 5. Ohmic Contacts
Handout 6. Interconnect Scaling
Handout 7. Power Modeling
Handout 8. Interconnect Thermal Modeling
Handout 9. Interconnect Scaling Thermal Issues
Handout 10. How to use TSUPREM4 (Tutorial)
Handout 11. Silicides
Handout 12. AluminumInterconnect Technology
Handout 13. Copper Interconnect Technology
Handout 14. Device Isolation Technology
Handout 15. Deposition and Planarization Technology

Lecture Slides
Trends in Integrated Circuits Technology
MOS Gate Dielectric Technology: Part 1
MOS Gate Dielectric Technology: Part 2
Shallow Junctions/Ohmic Contacts
Silicides & Metal gates
Interconnect Scaling
Aluminum Interconnect Technology
Copper Interconnect Technology
Low-K Dielectrics
Future Interconnect Technology
Future Devices part 1
Future Devices part 2
Future Devices part 3

Sample Exam
1. Exam Example 1
2. Exam Example 2

Useful Publications

General Technology Trends
1. Plummer and Griffin, "Material and Process Limits in Silicon VLSI Technology", IEEE Proceedings, March 2002.
2. Doyal et al., "Transistor Elements for 30nm Physical Gate Length and Beyond", Intel Technology Journal, May 2002
3. P. Wong, et al., "Nanoscale CMOS", IEEE Proceedings, April 1999.

Gate Dielectric
1. Momose, et al., "Feasibility of 1.5-nm Gate Oxide", IEEE Trans. Electron Dev., MARCH 1998.
2. Gupta et al., "Conduction in Gate Oxide", IEEE Electron Dev. Lett., Dec. 1997.
3. Schuegraf and Hu, "A Model for Gate Oxide Breakdown", IEEE Trans. Electron Dev., May 1994.
4. Yang and Saraswat, "Stress Effects in Gate Oxide", IEEE Trans. Electron Dev., April 2000.
5. Bhat et al., "NO Nitrided Gate Oxide", IEEE Trans. Electron Dev., May 1995.
6. Kim et al., "Nitride/Oxide Gate Dielectric", IEEE Trans. Electron Dev., May 1995.
7. Wilk et al., "High-k gate dielectrics", J. Applied Physics, May 2001.
8. Robertson, "High dielectric constant oxides", Eur. Phys. J. Appl. Phys. 28, 265?91 (2004).

Shallow Junctions
1. Kim, Park and Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime", Part I: Theoretical Derivation", IEEE Trans. Electron Dev., March 2002.
2. Kim, Park and Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime", Part II: Quantitative Analysis", IEEE Trans. Electron Dev., 1996.

Gate Electrode
1. Mann, et al.,, "Silicides and Local Interconnects.....", IBM J. Res. & Dev. July 1995.
2.Yeo, King, and Hu, "Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology", J. Appl. Phys., Vol. 92, No. 12, 15 December 2002.

Device Isolation
1. P. Smeys, "Exerpts from PhD Thesis", Stanford Univ. March 1996.

Interconnect
1. Havemann et al., "High-Performance Interconnects: An Integration Overview", IEEE Proceedings, May 2001.
2. A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 1 from PhD Thesis, Stanford Univ. March 1999.
3.A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 2 from PhD Thesis, Stanford Univ. March 1999.
4. A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 3 from PhD Thesis, Stanford Univ. March 1999.
5. P. Kapur, et al., "Technology and Reliability Constrained Future Copper Interconnects揚art I: Resistance Modeling", IEEE Trans. Electron Dev., 1996.
6. P. Kapur, et al., "Technology and Reliability Constrained Future Copper Interconnects揚art II: Performance Implications", IEEE Trans. Electron Dev., 1996.

Strained-Silicon Technologies
K. Rim, et. al., "Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs", IEEE IEDM 1995
K. Rim, et. al., "Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs", IEEE Trans. Electron Dev. 2000
T. Ghani, et. al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors", IEEE IEDM 2003
S. Thompson, et. al., "A Logic Nanotechnology Featuring Strained-Silicon", IEEE Electron. Dev. Lett., April 2004

Future Technologies
P. Wong, "Beyond the Conventional Transistor", IBM J. Res. & Dev. MARCH/MAY 2002.
J. Hutchby, et. al., "Extending the Road Beyond CMOS", IBM J. Res. & Dev. MARCH/MAY 2002.
Saraswat Group, "3D Integrated Circuits, Proc. IEEE, May 2001.
D. Miller, "Rationale and Challenges for Optical Interconnects to Electronic Chips", Proc.IEEE, June 2000.
A. Naeemi, et al., "Performance Comparison between Carbon Nanotube and Copper Interconnects for GSI", IEDM 2004.

Power
P. Kapur, et al., "Power Optimization of Future transistors and a resulting global comparison standard", IEDM 2004.
Shekar Borkar, "Digital Design for Low-Power Systems", IEDM Short Course 2005.
Scott Crowder, "Low Power CMOS Process Technology", IEDM Short Course, 2005.

==================================

CMOS and BiCMOS Process Integration Course

Day 1
- Conventional CMOS
  - Key components and parameters
  - Process overview and integration issues
  - Scaling and limitations
Day 2
- Mobility Enhancement Techniques
  - Strained silicon
  - Crystal orientation
- Gate stacks, high-k dielectrics
  - Gate conductor materials and properties
  - High-k materials and properties
  - Gate stack
- Ultra-shallow junctions
  - Impact of junction profile on parameters
  - Ultra-shallow junction formation
  - Trends
- Three-dimensional structures
  - FinFets
  - Multi-gates
  - Issues
- Interconnects
  - Low-k dielectrics
  - Copper
  - Trends
- Conventional BiCMOS: SiGe, SiGe:C
  - Key components and parameters
  - Process overview
  - Limitations
- Bipolar enhancement techniques
  - SiGe
  - SiGe:C
Day 3
- CMOS/BiCMOS reliability considerations
  - Electrostatic discharge
  - Electro-, stress-migration
  - Soft errors
  - Plasma damage
  - Dielectric reliability
  - Bias-temperature instabilities
  - Hot-carrier reliability
  - Burn-in
- Yield considerations
  - Yield detractors
  - Models
  - Monitors

===============================

Message from the Vice President, Science and Technology, IBM Research Division	T.-C. Chen

Preface	W. Haensch and M. Ieong, Guest Editors	p. 337

Silicon CMOS devices beyond scaling	W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti	p. 339

Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations	D. A. Antoniadis, I. Aberg, C. Ní Chléirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt	p. 363

Germanium channel MOSFETs: Opportunities and challenges	H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong	p. 377

Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges	E. P. Gusev, V. Narayanan, and M. M. Frank	p. 387

Emerging nanoscale silicon devices taking advantage of nanostructure physics	T. Hiramoto, M. Saitoh, and G. Tsutsui	p. 411

Optimizing CMOS technology for maximum performance	D. J. Frank, W. Haensch, G. Shahidi, and O. H. Dokumaci	p. 419

High-performance CMOS variability in the 65-nm regime and beyond	K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer	p. 433

Product-representative “at speed” test structures for CMOS characterization	M. B. Ketchen and M. Bhushan	p. 451

Ultralow-voltage, minimum-energy CMOS	S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester	p. 469

Three-dimensional integrated circuits	A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong	p. 491

Scaling the gate dielectric: Materials, integration and reliability

Introduction to Wafer Fab Processing: October 15-18, Austin, Texas

IC Packaging Technology and Challenges Course: October 15-16, Austin, Texas

IC Packaging Design and Modeling Course: October 17-19, Austin, Texas

CMOS and BiCMOS Process Integration Course: October 22-24, Austin, Texas

Failure and Yield Analysis Short Course: March 10-13, 2008, San Diego, California; May 26-29, 2008, Munich, Germany

Semiconductor Reliability Short Course: March 24-26, 2008, San Diego, California; May 19-21, 2008, Munich, Germany

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