Polysilicon Gate Depletion Effects in
Sub-Micron MOSFETs

It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion effects can safely be ignored. This article aims to quantify poly depletion effects for typical sub-micron device dimensions using ATHENA and ATLAS process and device simulators. The simulations show that the resultant effect on electrical characteristics often cannot be ignored.

These simulations show the importance of not defining the poly gate itself as the electrode when simulating MOSFETs. This would instruct the simulator to treat the poly-gate as a perfect conductor which would by definition not deplete. The accurate approach is to deposit metal onto the poly and define this metal layer as the electrode. This second approach has an added advantage in that it eliminates the need for the user to estimate the polysilicon work function since ATLAS can now calculate the actual workfunction from the doping profile. In a typical device the doping concentration in the poly at the end of processing can often yield a work function that differs significantly from the ideal case, resulting in shifted MOS electrical characteristics.

Modern Processing Techniques that Reduce Poly Doping.

A number of processing techniques currently used can reduce poly doping from the ideal saturated value. Some of the more common ones are discussed below.

(i) Silicide suck-out effects

The almost universally used silicide techniques for reducing poly and source-drain resistance have one slight disadvantage in that the process of forming the silicide "sucks out" a significant proportion of the dopant in the poly. The effect this has on device characteristics depends on how much dopant was in the poly prior to silicide formation.

(ii) Insufficient Implant Dose

In earlier technologies, the poly was doped in-situ as it was deposited, allowing total saturation of the poly with dopant. The effects of silicide "suck out" discussed above were therefore dramatically reduced. In modern processes, however, the in-situ method has been replaced with the deposition of nominally undoped poly, which is then implanted. Often the total implanted dose is significantly less than the total dose achieved with in-situ methods, enhancing the effects of silicide dopant reduction.

(iii) Compensation from P+ Implant

It is common practice, although not universal, to perform an unmasked P+ source-drain implant. This relies on the N+ poly doping being of significantly higher doping concentration, such that it remains N+ after being effectively partially compensated by the P+ implant. The P+ implant can reduce the effective N+ doping concentration in the poly quite significantly. In many processes P+ compensation changes the work function of the gate.

(iv) Dopant Evaporation

The activation anneal can result in significant evaporation of dopant, especially arsenic. The evaporation effect is correctly modeled in ATHENA. However, in order to accurately model dopant evaporation, the simulator input deck must be realistic. If the real device has a thin film of native oxide on the poly prior to the activation anneal, this will significantly reduce dopant evaporation. Be sure to deposit or grow the correct thickness of poly native oxide in ATHENA prior to the activation anneal for accurate simulation of the effect.

 

The Effects of Reduced Poly Doping

There are several effects of reduced doping in the poly that result in non-ideal electrical behavior in the final device. The main points are discussed below.

(a) the poly-silicon work function is increased from a near ideal value of 4.17eV achieved using in-situ poly doping to a more typical value of approximately 4.3 to 4.4eV for implanted/P+ compensated poly gates.

(b) the poly can become depleted during normal device operation. The resultant voltage drop will cause a loss of current drive in the final device.

(c) depletion in the poly can give rise to inaccurate measurement of oxide thickness if C-V curves are the source of the measurement. The effect is enhanced for thinner gate oxides. A further reduction in accuracy from C-V measurement originates from the quantum nature of the inversion region itself. In essence, the peak concentration of carriers in an accumulated device resides further away from the interface than is predicted by classical physics. This effect enhances the reduced capacitance measured, compounding the derived oxide thickness error.

Quantum effects are modeled in ATLAS and are activated by including the parameter QUANTUM in the MODELS statement.

Using ATHENA and ATLAS to Investigate the Effects of Poly Doping

The basic effects of poly doping can be simulated quickly and simply in 1D using typical Vt implant doses and energies. For investigation of poly depletion effects that occur whilst the device itself is inverted, the poly and channel doping are required to be of the same type. ie. N+ poly with n-type channel (the situation for a p-channel device) or P+ poly with a p-type channel. For similar levels of doping, the effects will be the same in either case.

Figure 1 shows the results of a simulation using p+ poly of various doping concentrations and a typical channel implant energy/dose of 20keV and 1e13/cm respectively. The silicon substrate was doped 1e15/cm p-type. The oxide was grown in wet O2 at 850C for three minutes resulting in a thickness of approximately 60Å (a typical value for 0.5µm technology). The three C-V plots in figure 1 were calculated in ATLAS simply by adding the parameters ac freq=1e6 to the solve statement which stipulated 0.2 volt steps from -10 to +10 volts.

Figure 1. C-V curves showing the effect of different doping concentrations in the poly gate.

Two further parameters were added to the solve statement for increased robustness in this case. These parameters were direct and previous. Direct is generally recommended for solving C-V curves whilst previous was added to use the previous simulation result as the initial guess for the next step in voltage. This overrides the default initial guess in ATLAS which makes a projection from the previous two points. This can cause convergence problems when the solution becomes noisy as in the inversion region.

The reason the solution can become noisy in inversion regions for 1D C-V solutions is that there is no source of the required excess minority carriers as would be the case in a 2D MOSFET device for example. The excess electrons in this case therefore have to be thermally generated in the simulator as they are in reality. It is the requirement of the simulator to accurately account for the total number of these thermally generated minority carriers that is the source of the noise.

Returning to Figure 1, it can be seen that even for a poly doping of 1e20/cm3, significant depletion occurs in the poly when the channel is accumulated. If a typical automated oxide thickness extract program used the maximum capacitance as the accumulated capacitance and calculated the oxide thickness from this value, it is clear a significant error would result. If the poly doping is reduced to 1e19/cm3. the poly itself goes into inversion, with a very large effect on the C-V curve and resulting MOSFET I-V curves. When the poly inverts, the noise returns in the calculated curve for the reasons discussed above.

Figure 2 proves that the poly has indeed inverted and shows a close up of the interface regions for a gate bias of -5 volts. Notice how the electron concentration in the P+ poly equals the hole concentration in the bulk of the poly (the usual definition for the onset of heavy inversion).

Figure 2. Carrier concentrations at the Oxide-Polysilicon
interface showing inversion in the polysilicon gate.

Figure 2 also demonstrates a very important point when simulating I-V curves in MOSFETs in general. Note the dimensions of the inversion and accumulated regions. The entire depletion region in the poly is significantly less than 100Å wide. The actual inverted region in a MOSFET channel (responsible for the drive current) is only approximately 10-30Å wide. It is therefore VERY important when accurately simulating I-V curves in MOSFETs that the mesh size in this region is no larger than 10Å per mesh point. If the inversion region is 30Å wide, a 10Å grid will still only provide 3 grid points in this sensitive region. In this example, the carrier concentration changes from 300 to 1x10 in less than 100Å at the poly-oxide interface.

Conclusion

For sub-micron simulations where polysilicon depletion is likely:

(1) Do not define the polysilicon gate region as the contact. Use an additional metal layer.

(2) In order to obtain accurate device simulation results, ensure that all relevant process steps are included and that the process steps are both realistic and accurate. Be especially careful to include any native oxide on the poly during thermal activation.

(3) Use a 10Å grid or smaller at the semiconductor-oxide, poly-oxide interfaces.