IDDQ testing is linked to the history of CMOS IC design and fabrication. In 1963 Frank Wanlass (Fairchild Semiconductor) originated and published the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby, it would draw practically nothing - just the leakage current. The concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) and its application to CMOS circuits was developed and demonstrated by Mark W. Levi in his ITC’1981 paper (“CMOS is most Testable”, Proceedings of ITC’81, pp. 217-220). It is therefore a fact that CMOS circuits with increased leakage current are defective.
 
IDDQ testing is a test technique based on measuring the Quiescent supply current of the device under test. A distinction needs to be made between application to technologies where the leakage current is neglect able and application to technologies were the leakage current is not neglectable. The traditional decision criterion - which is valid for technologies with low leakage currents - is based on the fact that a CMOS circuit does not draw any significant current when in a stable situation. In a quiescent state, only the leakage current flows, which is in most cases can be neglected. The fact that under certain conditions a significant current flows when the device under test is in a quiescent state, indicates the presence of a manufacturing defect in the circuit. Such a defect which causes a current increase, may have a direct influence on the functionality of the circuit (functional failure) or may affect the lifetime and reliability of the circuit negatively ((early) lifetime failure). Further info on IDDQ and limit setting can be found on the True IDDQ page.

For newer technologies, where the leakage current is not neglectable, a similar observation holds true. In such cases the base leakage cannot be neglected but needs to be considered as an offset level. The fact that under certain conditions there is an increase in the current flowing when the device under test is in a quiescent state, indicates the presence of a manufacturing defect in the circuit. Such a defect which causes a current increase, may have a direct influence on the functionality of the circuit (functional failure) or may affect the lifetime and reliability of the circuit negatively ((early) lifetime failure). By using a relative decision criterion (based on the comparison of the measured current to the base leakage current) defects can be screened reliably and effective, even in the presences of large background currents, provided suitable measurement tools are used.

IDDQ testing is a very sensitive technique, able to detect such problems in an early stage, even before they really harm the circuit. It is also a proper alternative to replace other, more expensive or more time-consuming test approaches, needed to guarantee the quality and reliability of the tested chip. In combination with emission spectroscopy and spectral analysis IDDQ is also a very powerful technique for defect location and defect diagnosis, obviating the need for fibbing.

The IDDQ test technique can be applied at wafer level, at packed device level, during incoming inspection, during life tests or even during on-line testing. Making use of an IDDQ test approach supported by the use of proper measurement instrumentation offers the following advantages :

• Increased product quality
• Replacement (or reduction) of Burn-in tests
• Elimination of early lifetime failures
• Increased product reliability
• Reduction of the overall test cost.
• Increase of engineering and failure analysis productivity.